From patchwork Tue Apr 13 22:59:20 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 51195 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id CBE98B7D45 for ; Thu, 29 Apr 2010 05:01:55 +1000 (EST) Received: from localhost ([127.0.0.1]:60007 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1O7CHc-0005PX-H8 for incoming@patchwork.ozlabs.org; Wed, 28 Apr 2010 14:46:52 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1O7C1e-0000Jd-Es for qemu-devel@nongnu.org; Wed, 28 Apr 2010 14:30:22 -0400 Received: from [140.186.70.92] (port=46619 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1O7C1W-0000Ff-Qe for qemu-devel@nongnu.org; Wed, 28 Apr 2010 14:30:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1O7C1Q-0004QR-VG for qemu-devel@nongnu.org; Wed, 28 Apr 2010 14:30:14 -0400 Received: from are.twiddle.net ([75.149.56.221]:36471) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1O7C1Q-0004PZ-Kv for qemu-devel@nongnu.org; Wed, 28 Apr 2010 14:30:08 -0400 Received: by are.twiddle.net (Postfix, from userid 5000) id DD093B08; Wed, 28 Apr 2010 11:30:05 -0700 (PDT) Message-Id: In-Reply-To: References: From: Richard Henderson Date: Tue, 13 Apr 2010 15:59:20 -0700 To: qemu-devel@nongnu.org X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 03/22] tcg-i386: Tidy ext8u and ext16u operations. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Define OPC_MOVZBL and OPC_MOVZWL. Factor opcode emission to separate functions. Don't restrict the input register to the low 4 "q" registers; emit an AND instead if needed. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c | 68 ++++++++++++++++++++++++++++++------------------ 1 files changed, 42 insertions(+), 26 deletions(-) diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c index 359f81b..2cc1191 100644 --- a/tcg/i386/tcg-target.c +++ b/tcg/i386/tcg-target.c @@ -161,6 +161,11 @@ static inline int tcg_target_const_match(tcg_target_long val, return 0; } +#define P_EXT 0x100 /* 0x0f opcode prefix */ + +#define OPC_MOVZBL (0xb6 | P_EXT) +#define OPC_MOVZWL (0xb7 | P_EXT) + #define ARITH_ADD 0 #define ARITH_OR 1 #define ARITH_ADC 2 @@ -194,8 +199,6 @@ static inline int tcg_target_const_match(tcg_target_long val, #define JCC_JLE 0xe #define JCC_JG 0xf -#define P_EXT 0x100 /* 0x0f opcode prefix */ - static const uint8_t tcg_cond_to_jcc[10] = { [TCG_COND_EQ] = JCC_JE, [TCG_COND_NE] = JCC_JNE, @@ -288,6 +291,27 @@ static inline void tcg_out_st(TCGContext *s, TCGType type, int arg, tcg_out_modrm_offset(s, 0x89, arg, arg1, arg2); } +static void tcg_out_ext8u(TCGContext *s, int dest, int src) +{ + if (src >= 4) { + tcg_out_mov(s, dest, src); + if (dest >= 4) { + tcg_out_modrm(s, 0x81, ARITH_AND, dest); + tcg_out32(s, 0xff); + return; + } + src = dest; + } + /* movzbl */ + tcg_out_modrm(s, OPC_MOVZBL, dest, src); +} + +static inline void tcg_out_ext16u(TCGContext *s, int dest, int src) +{ + /* movzwl */ + tcg_out_modrm(s, OPC_MOVZWL, dest, src); +} + static inline void tgen_arithi(TCGContext *s, int c, int r0, int32_t val, int cf) { if (!cf && ((c == ARITH_ADD && val == 1) || (c == ARITH_SUB && val == -1))) { @@ -300,11 +324,9 @@ static inline void tgen_arithi(TCGContext *s, int c, int r0, int32_t val, int cf tcg_out_modrm(s, 0x83, c, r0); tcg_out8(s, val); } else if (c == ARITH_AND && val == 0xffu && r0 < 4) { - /* movzbl */ - tcg_out_modrm(s, 0xb6 | P_EXT, r0, r0); + tcg_out_ext8u(s, r0, r0); } else if (c == ARITH_AND && val == 0xffffu) { - /* movzwl */ - tcg_out_modrm(s, 0xb7 | P_EXT, r0, r0); + tcg_out_ext16u(s, r0, r0); } else { tcg_out_modrm(s, 0x81, c, r0); tcg_out32(s, val); @@ -645,12 +667,10 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, tcg_out_modrm(s, 0xbf | P_EXT, data_reg, TCG_REG_EAX); break; case 0: - /* movzbl */ - tcg_out_modrm(s, 0xb6 | P_EXT, data_reg, TCG_REG_EAX); + tcg_out_ext8u(s, data_reg, TCG_REG_EAX); break; case 1: - /* movzwl */ - tcg_out_modrm(s, 0xb7 | P_EXT, data_reg, TCG_REG_EAX); + tcg_out_ext16u(s, data_reg, TCG_REG_EAX); break; case 2: default: @@ -690,7 +710,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, switch(opc) { case 0: /* movzbl */ - tcg_out_modrm_offset(s, 0xb6 | P_EXT, data_reg, r0, GUEST_BASE); + tcg_out_modrm_offset(s, OPC_MOVZBL, data_reg, r0, GUEST_BASE); break; case 0 | 4: /* movsbl */ @@ -698,7 +718,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, break; case 1: /* movzwl */ - tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, GUEST_BASE); + tcg_out_modrm_offset(s, OPC_MOVZWL, data_reg, r0, GUEST_BASE); if (bswap) { /* rolw $8, data_reg */ tcg_out8(s, 0x66); @@ -850,12 +870,10 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, } else { switch(opc) { case 0: - /* movzbl */ - tcg_out_modrm(s, 0xb6 | P_EXT, TCG_REG_EDX, data_reg); + tcg_out_ext8u(s, TCG_REG_EDX, data_reg); break; case 1: - /* movzwl */ - tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_EDX, data_reg); + tcg_out_ext16u(s, TCG_REG_EDX, data_reg); break; case 2: tcg_out_mov(s, TCG_REG_EDX, data_reg); @@ -881,12 +899,10 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, tcg_out_mov(s, TCG_REG_EDX, addr_reg2); switch(opc) { case 0: - /* movzbl */ - tcg_out_modrm(s, 0xb6 | P_EXT, TCG_REG_ECX, data_reg); + tcg_out_ext8u(s, TCG_REG_ECX, data_reg); break; case 1: - /* movzwl */ - tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_ECX, data_reg); + tcg_out_ext16u(s, TCG_REG_ECX, data_reg); break; case 2: tcg_out_mov(s, TCG_REG_ECX, data_reg); @@ -1022,7 +1038,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_ld8u_i32: /* movzbl */ - tcg_out_modrm_offset(s, 0xb6 | P_EXT, args[0], args[1], args[2]); + tcg_out_modrm_offset(s, OPC_MOVZBL, args[0], args[1], args[2]); break; case INDEX_op_ld8s_i32: /* movsbl */ @@ -1030,7 +1046,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_ld16u_i32: /* movzwl */ - tcg_out_modrm_offset(s, 0xb7 | P_EXT, args[0], args[1], args[2]); + tcg_out_modrm_offset(s, OPC_MOVZWL, args[0], args[1], args[2]); break; case INDEX_op_ld16s_i32: /* movswl */ @@ -1177,10 +1193,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_modrm(s, 0xbf | P_EXT, args[0], args[1]); break; case INDEX_op_ext8u_i32: - tcg_out_modrm(s, 0xb6 | P_EXT, args[0], args[1]); + tcg_out_ext8u(s, args[0], args[1]); break; case INDEX_op_ext16u_i32: - tcg_out_modrm(s, 0xb7 | P_EXT, args[0], args[1]); + tcg_out_ext16u(s, args[0], args[1]); break; case INDEX_op_setcond_i32: @@ -1275,8 +1291,8 @@ static const TCGTargetOpDef x86_op_defs[] = { { INDEX_op_ext8s_i32, { "r", "q" } }, { INDEX_op_ext16s_i32, { "r", "r" } }, - { INDEX_op_ext8u_i32, { "r", "q"} }, - { INDEX_op_ext16u_i32, { "r", "r"} }, + { INDEX_op_ext8u_i32, { "r", "r" } }, + { INDEX_op_ext16u_i32, { "r", "r" } }, { INDEX_op_setcond_i32, { "q", "r", "ri" } }, { INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } },