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[U-Boot,2/9] imx: mx6: ddr no support MMDC1 for i.MX6SL

Message ID 1439799065-12278-3-git-send-email-Peng.Fan@freescale.com
State Awaiting Upstream
Delegated to: Stefano Babic
Headers show

Commit Message

Peng Fan Aug. 17, 2015, 8:10 a.m. UTC 
i.MX 6SoloLite only supports MMDC0, so do not access MMDC1 for i.MX 6SL.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
---
 arch/arm/cpu/armv7/mx6/ddr.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

Comments

Stefano Babic Aug. 24, 2015, 8:02 a.m. UTC | #1 
On 17/08/2015 10:10, Peng Fan wrote:
> i.MX 6SoloLite only supports MMDC0, so do not access MMDC1 for i.MX 6SL.
> 
> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
> Cc: Stefano Babic <sbabic@denx.de>
> Cc: Tim Harvey <tharvey@gateworks.com>
> ---
>  arch/arm/cpu/armv7/mx6/ddr.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
> index b808627..28fa3cf 100644
> --- a/arch/arm/cpu/armv7/mx6/ddr.c
> +++ b/arch/arm/cpu/armv7/mx6/ddr.c
> @@ -288,7 +288,8 @@ void mx6sdl_dram_iocfg(unsigned width,
>  #define MR(val, ba, cmd, cs1) \
>  	((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
>  #define MMDC1(entry, value) do {					  \
> -	if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL))	  \
> +	if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL) && \
> +	    !is_cpu_type(MXC_CPU_MX6SL))				  \
>  		mmdc1->entry = value;					  \
>  	} while (0)
>  
> @@ -312,7 +313,8 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
>  	u16 mem_speed = ddr3_cfg->mem_speed;
>  
>  	mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
> -	if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL))
> +	if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL) &&
> +	    !is_cpu_type(MXC_CPU_MX6SL))
>  		mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
>  
>  	/* Limit mem_speed for MX6D/MX6Q */
> 

Reviewed-by: Stefano Babic <sbabic@denx.de>

Best regards,
Stefano Babic
diff mbox

Patch

diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index b808627..28fa3cf 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -288,7 +288,8 @@  void mx6sdl_dram_iocfg(unsigned width,
 #define MR(val, ba, cmd, cs1) \
 	((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
 #define MMDC1(entry, value) do {					  \
-	if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL))	  \
+	if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL) && \
+	    !is_cpu_type(MXC_CPU_MX6SL))				  \
 		mmdc1->entry = value;					  \
 	} while (0)
 
@@ -312,7 +313,8 @@  void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 	u16 mem_speed = ddr3_cfg->mem_speed;
 
 	mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
-	if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL))
+	if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL) &&
+	    !is_cpu_type(MXC_CPU_MX6SL))
 		mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
 
 	/* Limit mem_speed for MX6D/MX6Q */