diff mbox

[4/4] target-sparc: Convert to VMStateDescription

Message ID 1439210072-11028-5-git-send-email-peter.maydell@linaro.org
State New
Headers show

Commit Message

Peter Maydell Aug. 10, 2015, 12:34 p.m. UTC 
From: Juan Quintela <quintela@redhat.com>

Convert the SPARC CPU from cpu_load/save functions to VMStateDescription.
Note that this is a migration compatibility break (which is OK as
we don't try to support cross-version migration on SPARC).

Signed-off-by: Juan Quintela <quintela@redhat.com>
[PMM:
 * Rebase and update to apply to master
 * Register via dc->vmsd
 * VMSTATE_STRUCT_POINTER now takes type, not pointer-to-type
 * QEMUTimer* are migrated via VMSTATE_TIMER_PTR
 * Squash in another patch from Juan that arrayifies the state
   descriptions for immuregs, dmmuregs, itlb and dtlb, since we're
   going to break VM state compatibility anyway
 * Put CPUTimer vmstate struct inside TARGET_SPARC64 ifdef
 * Save the whole of env.regbase rather than having a complicated
   scheme for only saving the part we're using
 * Convert handling of PSR to use a vmstate_psr, like Alpha and ARM
]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/sparc64/sun4u.c     |  20 ---
 target-sparc/cpu-qom.h |   4 +
 target-sparc/cpu.c     |   1 +
 target-sparc/cpu.h     |   6 -
 target-sparc/machine.c | 359 ++++++++++++++++++++++---------------------------
 5 files changed, 167 insertions(+), 223 deletions(-)

Comments

Paolo Bonzini Aug. 18, 2015, 3:15 p.m. UTC | #1 
On 10/08/2015 05:34, Peter Maydell wrote:
> -    // if env->cwp == env->nwindows - 1, this will set the ins of the last
> -    // window as the outs of the first window
> -    cpu_set_cwp(env, env->cwp);

Out of curiosity, what migrates env->cwp for SPARC64?

Paolo
diff mbox

Patch

diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c
index 30cfa0e..93dca10 100644
--- a/hw/sparc64/sun4u.c
+++ b/hw/sparc64/sun4u.c
@@ -358,26 +358,6 @@  typedef struct ResetData {
     uint64_t prom_addr;
 } ResetData;
 
-void cpu_put_timer(QEMUFile *f, CPUTimer *s)
-{
-    qemu_put_be32s(f, &s->frequency);
-    qemu_put_be32s(f, &s->disabled);
-    qemu_put_be64s(f, &s->disabled_mask);
-    qemu_put_sbe64s(f, &s->clock_offset);
-
-    timer_put(f, s->qtimer);
-}
-
-void cpu_get_timer(QEMUFile *f, CPUTimer *s)
-{
-    qemu_get_be32s(f, &s->frequency);
-    qemu_get_be32s(f, &s->disabled);
-    qemu_get_be64s(f, &s->disabled_mask);
-    qemu_get_sbe64s(f, &s->clock_offset);
-
-    timer_get(f, s->qtimer);
-}
-
 static CPUTimer *cpu_timer_create(const char *name, SPARCCPU *cpu,
                                   QEMUBHFunc *cb, uint32_t frequency,
                                   uint64_t disabled_mask)
diff --git a/target-sparc/cpu-qom.h b/target-sparc/cpu-qom.h
index 477c4d5..5096b10 100644
--- a/target-sparc/cpu-qom.h
+++ b/target-sparc/cpu-qom.h
@@ -75,6 +75,10 @@  static inline SPARCCPU *sparc_env_get_cpu(CPUSPARCState *env)
 
 #define ENV_OFFSET offsetof(SPARCCPU, env)
 
+#ifndef CONFIG_USER_ONLY
+extern const struct VMStateDescription vmstate_sparc_cpu;
+#endif
+
 void sparc_cpu_do_interrupt(CPUState *cpu);
 void sparc_cpu_dump_state(CPUState *cpu, FILE *f,
                           fprintf_function cpu_fprintf, int flags);
diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
index 9528e3a..aea0a99 100644
--- a/target-sparc/cpu.c
+++ b/target-sparc/cpu.c
@@ -847,6 +847,7 @@  static void sparc_cpu_class_init(ObjectClass *oc, void *data)
     cc->do_unassigned_access = sparc_cpu_unassigned_access;
     cc->do_unaligned_access = sparc_cpu_do_unaligned_access;
     cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
+    dc->vmsd = &vmstate_sparc_cpu;
 #endif
 
 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 9a4a010..bf4164e 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -377,10 +377,6 @@  struct CPUTimer
 
 typedef struct CPUTimer CPUTimer;
 
-struct QEMUFile;
-void cpu_put_timer(struct QEMUFile *f, CPUTimer *s);
-void cpu_get_timer(struct QEMUFile *f, CPUTimer *s);
-
 typedef struct CPUSPARCState CPUSPARCState;
 
 struct CPUSPARCState {
@@ -603,8 +599,6 @@  int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
 #define cpu_signal_handler cpu_sparc_signal_handler
 #define cpu_list sparc_cpu_list
 
-#define CPU_SAVE_VERSION 7
-
 /* MMU modes definitions */
 #if defined (TARGET_SPARC64)
 #define MMU_USER_IDX   0
diff --git a/target-sparc/machine.c b/target-sparc/machine.c
index 7d03759..0354b1e 100644
--- a/target-sparc/machine.c
+++ b/target-sparc/machine.c
@@ -4,214 +4,179 @@ 
 
 #include "cpu.h"
 
-void cpu_save(QEMUFile *f, void *opaque)
-{
-    CPUSPARCState *env = opaque;
-    int i;
-    uint32_t tmp;
-
-    // if env->cwp == env->nwindows - 1, this will set the ins of the last
-    // window as the outs of the first window
-    cpu_set_cwp(env, env->cwp);
+#ifdef TARGET_SPARC64
+static const VMStateDescription vmstate_cpu_timer = {
+    .name = "cpu_timer",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .minimum_version_id_old = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(frequency, CPUTimer),
+        VMSTATE_UINT32(disabled, CPUTimer),
+        VMSTATE_UINT64(disabled_mask, CPUTimer),
+        VMSTATE_INT64(clock_offset, CPUTimer),
+        VMSTATE_TIMER_PTR(qtimer, CPUTimer),
+        VMSTATE_END_OF_LIST()
+    }
+};
 
-    for(i = 0; i < 8; i++)
-        qemu_put_betls(f, &env->gregs[i]);
-    qemu_put_be32s(f, &env->nwindows);
-    for(i = 0; i < env->nwindows * 16; i++)
-        qemu_put_betls(f, &env->regbase[i]);
+#define VMSTATE_CPU_TIMER(_f, _s)                             \
+    VMSTATE_STRUCT_POINTER(_f, _s, vmstate_cpu_timer, CPUTimer)
 
-    /* FPU */
-    for (i = 0; i < TARGET_DPREGS; i++) {
-        qemu_put_be32(f, env->fpr[i].l.upper);
-        qemu_put_be32(f, env->fpr[i].l.lower);
+static const VMStateDescription vmstate_trap_state = {
+    .name = "trap_state",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .minimum_version_id_old = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT64(tpc, trap_state),
+        VMSTATE_UINT64(tnpc, trap_state),
+        VMSTATE_UINT64(tstate, trap_state),
+        VMSTATE_UINT32(tt, trap_state),
+        VMSTATE_END_OF_LIST()
     }
+};
 
-    qemu_put_betls(f, &env->pc);
-    qemu_put_betls(f, &env->npc);
-    qemu_put_betls(f, &env->y);
-    tmp = cpu_get_psr(env);
-    qemu_put_be32(f, tmp);
-    qemu_put_betls(f, &env->fsr);
-    qemu_put_betls(f, &env->tbr);
-    tmp = env->interrupt_index;
-    qemu_put_be32(f, tmp);
-    qemu_put_be32s(f, &env->pil_in);
-#ifndef TARGET_SPARC64
-    qemu_put_be32s(f, &env->wim);
-    /* MMU */
-    for (i = 0; i < 32; i++)
-        qemu_put_be32s(f, &env->mmuregs[i]);
-    for (i = 0; i < 4; i++) {
-        qemu_put_be64s(f, &env->mxccdata[i]);
-    }
-    for (i = 0; i < 8; i++) {
-        qemu_put_be64s(f, &env->mxccregs[i]);
-    }
-    qemu_put_be32s(f, &env->mmubpctrv);
-    qemu_put_be32s(f, &env->mmubpctrc);
-    qemu_put_be32s(f, &env->mmubpctrs);
-    qemu_put_be64s(f, &env->mmubpaction);
-    for (i = 0; i < 4; i++) {
-        qemu_put_be64s(f, &env->mmubpregs[i]);
-    }
-#else
-    qemu_put_be64s(f, &env->lsu);
-    for (i = 0; i < 16; i++) {
-        qemu_put_be64s(f, &env->immuregs[i]);
-        qemu_put_be64s(f, &env->dmmuregs[i]);
+static const VMStateDescription vmstate_tlb_entry = {
+    .name = "tlb_entry",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .minimum_version_id_old = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT64(tag, SparcTLBEntry),
+        VMSTATE_UINT64(tte, SparcTLBEntry),
+        VMSTATE_END_OF_LIST()
     }
-    for (i = 0; i < 64; i++) {
-        qemu_put_be64s(f, &env->itlb[i].tag);
-        qemu_put_be64s(f, &env->itlb[i].tte);
-        qemu_put_be64s(f, &env->dtlb[i].tag);
-        qemu_put_be64s(f, &env->dtlb[i].tte);
-    }
-    qemu_put_be32s(f, &env->mmu_version);
-    for (i = 0; i < MAXTL_MAX; i++) {
-        qemu_put_be64s(f, &env->ts[i].tpc);
-        qemu_put_be64s(f, &env->ts[i].tnpc);
-        qemu_put_be64s(f, &env->ts[i].tstate);
-        qemu_put_be32s(f, &env->ts[i].tt);
-    }
-    qemu_put_be32s(f, &env->xcc);
-    qemu_put_be32s(f, &env->asi);
-    qemu_put_be32s(f, &env->pstate);
-    qemu_put_be32s(f, &env->tl);
-    qemu_put_be32s(f, &env->cansave);
-    qemu_put_be32s(f, &env->canrestore);
-    qemu_put_be32s(f, &env->otherwin);
-    qemu_put_be32s(f, &env->wstate);
-    qemu_put_be32s(f, &env->cleanwin);
-    for (i = 0; i < 8; i++)
-        qemu_put_be64s(f, &env->agregs[i]);
-    for (i = 0; i < 8; i++)
-        qemu_put_be64s(f, &env->bgregs[i]);
-    for (i = 0; i < 8; i++)
-        qemu_put_be64s(f, &env->igregs[i]);
-    for (i = 0; i < 8; i++)
-        qemu_put_be64s(f, &env->mgregs[i]);
-    qemu_put_be64s(f, &env->fprs);
-    qemu_put_be64s(f, &env->tick_cmpr);
-    qemu_put_be64s(f, &env->stick_cmpr);
-    cpu_put_timer(f, env->tick);
-    cpu_put_timer(f, env->stick);
-    qemu_put_be64s(f, &env->gsr);
-    qemu_put_be32s(f, &env->gl);
-    qemu_put_be64s(f, &env->hpstate);
-    for (i = 0; i < MAXTL_MAX; i++)
-        qemu_put_be64s(f, &env->htstate[i]);
-    qemu_put_be64s(f, &env->hintp);
-    qemu_put_be64s(f, &env->htba);
-    qemu_put_be64s(f, &env->hver);
-    qemu_put_be64s(f, &env->hstick_cmpr);
-    qemu_put_be64s(f, &env->ssr);
-    cpu_put_timer(f, env->hstick);
+};
 #endif
+
+static int get_psr(QEMUFile *f, void *opaque, size_t size)
+{
+    CPUSPARCState *env = opaque;
+    uint32_t val = qemu_get_be32(f);
+
+    /* needed to ensure that the wrapping registers are correctly updated */
+    env->cwp = 0;
+    cpu_put_psr_raw(env, val);
+
+    return 0;
 }
 
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
+static void put_psr(QEMUFile *f, void *opaque, size_t size)
 {
     CPUSPARCState *env = opaque;
-    SPARCCPU *cpu = sparc_env_get_cpu(env);
-    int i;
-    uint32_t tmp;
-
-    if (version_id < 6)
-        return -EINVAL;
-    for(i = 0; i < 8; i++)
-        qemu_get_betls(f, &env->gregs[i]);
-    qemu_get_be32s(f, &env->nwindows);
-    for(i = 0; i < env->nwindows * 16; i++)
-        qemu_get_betls(f, &env->regbase[i]);
-
-    /* FPU */
-    for (i = 0; i < TARGET_DPREGS; i++) {
-        env->fpr[i].l.upper = qemu_get_be32(f);
-        env->fpr[i].l.lower = qemu_get_be32(f);
-    }
+    uint32_t val;
+
+    val = cpu_get_psr(env);
 
-    qemu_get_betls(f, &env->pc);
-    qemu_get_betls(f, &env->npc);
-    qemu_get_betls(f, &env->y);
-    tmp = qemu_get_be32(f);
-    env->cwp = 0; /* needed to ensure that the wrapping registers are
-                     correctly updated */
-    cpu_put_psr(env, tmp);
-    qemu_get_betls(f, &env->fsr);
-    qemu_get_betls(f, &env->tbr);
-    tmp = qemu_get_be32(f);
-    env->interrupt_index = tmp;
-    qemu_get_be32s(f, &env->pil_in);
+    qemu_put_be32(f, val);
+}
+
+static const VMStateInfo vmstate_psr = {
+    .name = "psr",
+    .get = get_psr,
+    .put = put_psr,
+};
+
+static void cpu_pre_save(void *opaque)
+{
+    CPUSPARCState *env = opaque;
+
+    /* if env->cwp == env->nwindows - 1, this will set the ins of the last
+     * window as the outs of the first window
+     */
+    cpu_set_cwp(env, env->cwp);
+}
+
+static const VMStateDescription vmstate_sparc_env = {
+    .name = "env",
+    .version_id = 8,
+    .minimum_version_id = 8,
+    .minimum_version_id_old = 8,
+    .pre_save = cpu_pre_save,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINTTL_ARRAY(gregs, CPUSPARCState, 8),
+        VMSTATE_UINT32(nwindows, CPUSPARCState),
+        VMSTATE_UINTTL_ARRAY(regbase, CPUSPARCState, MAX_NWINDOWS * 16 + 8),
+        VMSTATE_CPUDOUBLE_ARRAY(fpr, CPUSPARCState, TARGET_DPREGS),
+        VMSTATE_UINTTL(pc, CPUSPARCState),
+        VMSTATE_UINTTL(npc, CPUSPARCState),
+        VMSTATE_UINTTL(y, CPUSPARCState),
+        {
+
+            .name = "psr",
+            .version_id = 0,
+            .size = sizeof(uint32_t),
+            .info = &vmstate_psr,
+            .flags = VMS_SINGLE,
+            .offset = 0,
+        },
+        VMSTATE_UINTTL(fsr, CPUSPARCState),
+        VMSTATE_UINTTL(tbr, CPUSPARCState),
+        VMSTATE_INT32(interrupt_index, CPUSPARCState),
+        VMSTATE_UINT32(pil_in, CPUSPARCState),
 #ifndef TARGET_SPARC64
-    qemu_get_be32s(f, &env->wim);
-    /* MMU */
-    for (i = 0; i < 32; i++)
-        qemu_get_be32s(f, &env->mmuregs[i]);
-    for (i = 0; i < 4; i++) {
-        qemu_get_be64s(f, &env->mxccdata[i]);
-    }
-    for (i = 0; i < 8; i++) {
-        qemu_get_be64s(f, &env->mxccregs[i]);
-    }
-    qemu_get_be32s(f, &env->mmubpctrv);
-    qemu_get_be32s(f, &env->mmubpctrc);
-    qemu_get_be32s(f, &env->mmubpctrs);
-    qemu_get_be64s(f, &env->mmubpaction);
-    for (i = 0; i < 4; i++) {
-        qemu_get_be64s(f, &env->mmubpregs[i]);
-    }
+        /* MMU */
+        VMSTATE_UINT32(wim, CPUSPARCState),
+        VMSTATE_UINT32_ARRAY(mmuregs, CPUSPARCState, 32),
+        VMSTATE_UINT64_ARRAY(mxccdata, CPUSPARCState, 4),
+        VMSTATE_UINT64_ARRAY(mxccregs, CPUSPARCState, 8),
+        VMSTATE_UINT32(mmubpctrv, CPUSPARCState),
+        VMSTATE_UINT32(mmubpctrc, CPUSPARCState),
+        VMSTATE_UINT32(mmubpctrs, CPUSPARCState),
+        VMSTATE_UINT64(mmubpaction, CPUSPARCState),
+        VMSTATE_UINT64_ARRAY(mmubpregs, CPUSPARCState, 4),
 #else
-    qemu_get_be64s(f, &env->lsu);
-    for (i = 0; i < 16; i++) {
-        qemu_get_be64s(f, &env->immuregs[i]);
-        qemu_get_be64s(f, &env->dmmuregs[i]);
-    }
-    for (i = 0; i < 64; i++) {
-        qemu_get_be64s(f, &env->itlb[i].tag);
-        qemu_get_be64s(f, &env->itlb[i].tte);
-        qemu_get_be64s(f, &env->dtlb[i].tag);
-        qemu_get_be64s(f, &env->dtlb[i].tte);
-    }
-    qemu_get_be32s(f, &env->mmu_version);
-    for (i = 0; i < MAXTL_MAX; i++) {
-        qemu_get_be64s(f, &env->ts[i].tpc);
-        qemu_get_be64s(f, &env->ts[i].tnpc);
-        qemu_get_be64s(f, &env->ts[i].tstate);
-        qemu_get_be32s(f, &env->ts[i].tt);
-    }
-    qemu_get_be32s(f, &env->xcc);
-    qemu_get_be32s(f, &env->asi);
-    qemu_get_be32s(f, &env->pstate);
-    qemu_get_be32s(f, &env->tl);
-    qemu_get_be32s(f, &env->cansave);
-    qemu_get_be32s(f, &env->canrestore);
-    qemu_get_be32s(f, &env->otherwin);
-    qemu_get_be32s(f, &env->wstate);
-    qemu_get_be32s(f, &env->cleanwin);
-    for (i = 0; i < 8; i++)
-        qemu_get_be64s(f, &env->agregs[i]);
-    for (i = 0; i < 8; i++)
-        qemu_get_be64s(f, &env->bgregs[i]);
-    for (i = 0; i < 8; i++)
-        qemu_get_be64s(f, &env->igregs[i]);
-    for (i = 0; i < 8; i++)
-        qemu_get_be64s(f, &env->mgregs[i]);
-    qemu_get_be64s(f, &env->fprs);
-    qemu_get_be64s(f, &env->tick_cmpr);
-    qemu_get_be64s(f, &env->stick_cmpr);
-    cpu_get_timer(f, env->tick);
-    cpu_get_timer(f, env->stick);
-    qemu_get_be64s(f, &env->gsr);
-    qemu_get_be32s(f, &env->gl);
-    qemu_get_be64s(f, &env->hpstate);
-    for (i = 0; i < MAXTL_MAX; i++)
-        qemu_get_be64s(f, &env->htstate[i]);
-    qemu_get_be64s(f, &env->hintp);
-    qemu_get_be64s(f, &env->htba);
-    qemu_get_be64s(f, &env->hver);
-    qemu_get_be64s(f, &env->hstick_cmpr);
-    qemu_get_be64s(f, &env->ssr);
-    cpu_get_timer(f, env->hstick);
+        VMSTATE_UINT64(lsu, CPUSPARCState),
+        VMSTATE_UINT64_ARRAY(immuregs, CPUSPARCState, 16),
+        VMSTATE_UINT64_ARRAY(dmmuregs, CPUSPARCState, 16),
+        VMSTATE_STRUCT_ARRAY(itlb, CPUSPARCState, 64, 0,
+                             vmstate_tlb_entry, SparcTLBEntry),
+        VMSTATE_STRUCT_ARRAY(dtlb, CPUSPARCState, 64, 0,
+                             vmstate_tlb_entry, SparcTLBEntry),
+        VMSTATE_UINT32(mmu_version, CPUSPARCState),
+        VMSTATE_STRUCT_ARRAY(ts, CPUSPARCState, MAXTL_MAX, 0,
+                             vmstate_trap_state, trap_state),
+        VMSTATE_UINT32(xcc, CPUSPARCState),
+        VMSTATE_UINT32(asi, CPUSPARCState),
+        VMSTATE_UINT32(pstate, CPUSPARCState),
+        VMSTATE_UINT32(tl, CPUSPARCState),
+        VMSTATE_UINT32(cansave, CPUSPARCState),
+        VMSTATE_UINT32(canrestore, CPUSPARCState),
+        VMSTATE_UINT32(otherwin, CPUSPARCState),
+        VMSTATE_UINT32(wstate, CPUSPARCState),
+        VMSTATE_UINT32(cleanwin, CPUSPARCState),
+        VMSTATE_UINT64_ARRAY(agregs, CPUSPARCState, 8),
+        VMSTATE_UINT64_ARRAY(bgregs, CPUSPARCState, 8),
+        VMSTATE_UINT64_ARRAY(igregs, CPUSPARCState, 8),
+        VMSTATE_UINT64_ARRAY(mgregs, CPUSPARCState, 8),
+        VMSTATE_UINT64(fprs, CPUSPARCState),
+        VMSTATE_UINT64(tick_cmpr, CPUSPARCState),
+        VMSTATE_UINT64(stick_cmpr, CPUSPARCState),
+        VMSTATE_CPU_TIMER(tick, CPUSPARCState),
+        VMSTATE_CPU_TIMER(stick, CPUSPARCState),
+        VMSTATE_UINT64(gsr, CPUSPARCState),
+        VMSTATE_UINT32(gl, CPUSPARCState),
+        VMSTATE_UINT64(hpstate, CPUSPARCState),
+        VMSTATE_UINT64_ARRAY(htstate, CPUSPARCState, MAXTL_MAX),
+        VMSTATE_UINT64(hintp, CPUSPARCState),
+        VMSTATE_UINT64(htba, CPUSPARCState),
+        VMSTATE_UINT64(hver, CPUSPARCState),
+        VMSTATE_UINT64(hstick_cmpr, CPUSPARCState),
+        VMSTATE_UINT64(ssr, CPUSPARCState),
+        VMSTATE_CPU_TIMER(hstick, CPUSPARCState),
 #endif
-    return 0;
-}
+        VMSTATE_END_OF_LIST()
+    },
+};
+
+const VMStateDescription vmstate_sparc_cpu = {
+    .name = "cpu",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_CPU(),
+        VMSTATE_STRUCT(env, SPARCCPU, 1, vmstate_sparc_env, CPUSPARCState),
+        VMSTATE_END_OF_LIST()
+    }
+};