From patchwork Mon Oct 20 09:09:47 2008 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: S3C24xx NAND: Correct tacls_max for S3C2410 Date: Sun, 19 Oct 2008 23:09:47 -0000 From: Harald Welte X-Patchwork-Id: 5056 Message-Id: <20081020090947.GZ1048@prithivi.gnumonks.org> To: Ben Dooks Cc: linux-mtd@lists.infradead.org At least according to my S3C2410X manual, the maximum tacls setting for the 2410 is 8, not 4. S3C2410 is therefore like the S3C2412 (and 2443), not like 2440 and 2442. Signed-of-by: Harald Welte diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c index 4413d76..251f7a3 100644 --- a/drivers/mtd/nand/s3c2410.c +++ b/drivers/mtd/nand/s3c2410.c @@ -183,10 +183,20 @@ static int s3c2410_nand_inithw(struct s3c2410_nand_info *info, { struct s3c2410_platform_nand *plat = to_nand_plat(pdev); unsigned long clkrate = clk_get_rate(info->clk); - int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4; + int tacls_max; int tacls, twrph0, twrph1; unsigned long cfg = 0; + switch (info->cpu_type) { + case TYPE_S3C2410: + case TYPE_S3C2412: + tacls_max = 8; + break; + default: + tacls_max = 4; + break; + } + /* calculate the timing information for the controller */ clkrate /= 1000; /* turn clock into kHz for ease of use */