From patchwork Mon Apr 19 09:43:15 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshiaki Tamura X-Patchwork-Id: 50434 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 3496CB7D0B for ; Mon, 19 Apr 2010 20:08:18 +1000 (EST) Received: from localhost ([127.0.0.1]:50874 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1O3nsB-000313-Gt for incoming@patchwork.ozlabs.org; Mon, 19 Apr 2010 06:06:35 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1O3nau-00070C-0a for qemu-devel@nongnu.org; Mon, 19 Apr 2010 05:48:44 -0400 Received: from [140.186.70.92] (port=52039 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1O3nap-0006wy-3j for qemu-devel@nongnu.org; Mon, 19 Apr 2010 05:48:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1O3nah-0007ug-87 for qemu-devel@nongnu.org; Mon, 19 Apr 2010 05:48:38 -0400 Received: from sh.osrg.net ([192.16.179.4]:33420) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1O3nag-0007t4-M6 for qemu-devel@nongnu.org; Mon, 19 Apr 2010 05:48:31 -0400 Received: from fs.osrg.net (postfix@fs.osrg.net [10.0.0.12]) by sh.osrg.net (8.14.3/8.14.3/OSRG-NET) with ESMTP id o3J9mKHw008808; Mon, 19 Apr 2010 18:48:21 +0900 Received: from localhost (hype-wd0.osrg.net [10.72.1.16]) by fs.osrg.net (Postfix) with ESMTP id 50B953E02F0; Mon, 19 Apr 2010 18:48:20 +0900 (JST) From: Yoshiaki Tamura To: qemu-devel@nongnu.org Date: Mon, 19 Apr 2010 18:43:15 +0900 Message-Id: <1271670198-12793-4-git-send-email-tamura.yoshiaki@lab.ntt.co.jp> X-Mailer: git-send-email 1.7.0.31.g1df487 In-Reply-To: <1271670198-12793-1-git-send-email-tamura.yoshiaki@lab.ntt.co.jp> References: <1271670198-12793-1-git-send-email-tamura.yoshiaki@lab.ntt.co.jp> X-Dispatcher: imput version 20070423(IM149) Lines: 140 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-3.0 (sh.osrg.net [192.16.179.4]); Mon, 19 Apr 2010 18:48:22 +0900 (JST) X-Virus-Scanned: clamav-milter 0.95.3 at sh X-Virus-Status: Clean X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: aliguori@us.ibm.com, ohmura.kei@lab.ntt.co.jp, mtosatti@redhat.com, Yoshiaki Tamura , avi@redhat.com Subject: [Qemu-devel] [PATCH v3 3/6] Modifies wrapper functions for byte-based phys_ram_dirty bitmap to bit-based phys_ram_dirty bitmap. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org MASTER works as a buffer, and upon get_diry() or get_dirty_flags(), it calls cpu_physical_memory_sync_master() to update VGA and MIGRATION. Signed-off-by: Yoshiaki Tamura --- cpu-all.h | 96 +++++++++++++++++++++++++++++++++++++++++++++++++++--------- 1 files changed, 81 insertions(+), 15 deletions(-) diff --git a/cpu-all.h b/cpu-all.h index 8c2d678..2478887 100644 --- a/cpu-all.h +++ b/cpu-all.h @@ -907,43 +907,109 @@ static inline int idx_to_flag(int idx) /* read dirty bit (return 0 or 1) */ static inline int cpu_physical_memory_is_dirty(ram_addr_t addr) { - return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff; + unsigned long mask; + ram_addr_t index = (addr >> TARGET_PAGE_BITS) / HOST_LONG_BITS; + int offset = (addr >> TARGET_PAGE_BITS) & (HOST_LONG_BITS - 1); + + mask = 1UL << offset; + return (phys_ram_dirty[MASTER_DIRTY_IDX][index] & mask) == mask; +} + +static inline void cpu_physical_memory_sync_master(ram_addr_t index) +{ + if (phys_ram_dirty[MASTER_DIRTY_IDX][index]) { + phys_ram_dirty[VGA_DIRTY_IDX][index] + |= phys_ram_dirty[MASTER_DIRTY_IDX][index]; + phys_ram_dirty[MIGRATION_DIRTY_IDX][index] + |= phys_ram_dirty[MASTER_DIRTY_IDX][index]; + phys_ram_dirty[MASTER_DIRTY_IDX][index] = 0UL; + } } static inline int cpu_physical_memory_get_dirty_flags(ram_addr_t addr) { - return phys_ram_dirty[addr >> TARGET_PAGE_BITS]; + unsigned long mask; + ram_addr_t index = (addr >> TARGET_PAGE_BITS) / HOST_LONG_BITS; + int offset = (addr >> TARGET_PAGE_BITS) & (HOST_LONG_BITS - 1); + int ret = 0, i; + + mask = 1UL << offset; + cpu_physical_memory_sync_master(index); + + for (i = VGA_DIRTY_IDX; i <= MIGRATION_DIRTY_IDX; i++) { + if (phys_ram_dirty[i][index] & mask) { + ret |= idx_to_flag(i); + } + } + + return ret; +} + +static inline int cpu_physical_memory_get_dirty_idx(ram_addr_t addr, + int dirty_idx) +{ + unsigned long mask; + ram_addr_t index = (addr >> TARGET_PAGE_BITS) / HOST_LONG_BITS; + int offset = (addr >> TARGET_PAGE_BITS) & (HOST_LONG_BITS - 1); + + mask = 1UL << offset; + cpu_physical_memory_sync_master(index); + return (phys_ram_dirty[dirty_idx][index] & mask) == mask; } static inline int cpu_physical_memory_get_dirty(ram_addr_t addr, int dirty_flags) { - return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags; + return cpu_physical_memory_get_dirty_idx(addr, flag_to_idx(dirty_flags)); } static inline void cpu_physical_memory_set_dirty(ram_addr_t addr) { - phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff; + unsigned long mask; + ram_addr_t index = (addr >> TARGET_PAGE_BITS) / HOST_LONG_BITS; + int offset = (addr >> TARGET_PAGE_BITS) & (HOST_LONG_BITS - 1); + + mask = 1UL << offset; + phys_ram_dirty[MASTER_DIRTY_IDX][index] |= mask; } -static inline int cpu_physical_memory_set_dirty_flags(ram_addr_t addr, - int dirty_flags) +static inline void cpu_physical_memory_set_dirty_range(ram_addr_t addr, + unsigned long mask) { - return phys_ram_dirty[addr >> TARGET_PAGE_BITS] |= dirty_flags; + ram_addr_t index = (addr >> TARGET_PAGE_BITS) / HOST_LONG_BITS; + + phys_ram_dirty[MASTER_DIRTY_IDX][index] |= mask; +} + +static inline void cpu_physical_memory_set_dirty_flags(ram_addr_t addr, + int dirty_flags) +{ + unsigned long mask; + ram_addr_t index = (addr >> TARGET_PAGE_BITS) / HOST_LONG_BITS; + int offset = (addr >> TARGET_PAGE_BITS) & (HOST_LONG_BITS - 1); + + mask = 1UL << offset; + phys_ram_dirty[MASTER_DIRTY_IDX][index] |= mask; + + if (dirty_flags & CODE_DIRTY_FLAG) { + phys_ram_dirty[CODE_DIRTY_IDX][index] |= mask; + } } static inline void cpu_physical_memory_mask_dirty_range(ram_addr_t start, - int length, + unsigned long length, int dirty_flags) { - int i, mask, len; - uint8_t *p; + ram_addr_t addr = start, index; + unsigned long mask; + int offset, i; - len = length >> TARGET_PAGE_BITS; - mask = ~dirty_flags; - p = phys_ram_dirty + (start >> TARGET_PAGE_BITS); - for (i = 0; i < len; i++) - p[i] &= mask; + for (i = 0; i < length; i += TARGET_PAGE_SIZE) { + index = ((addr + i) >> TARGET_PAGE_BITS) / HOST_LONG_BITS; + offset = ((addr + i) >> TARGET_PAGE_BITS) & (HOST_LONG_BITS - 1); + mask = ~(1UL << offset); + phys_ram_dirty[flag_to_idx(dirty_flags)][index] &= mask; + } } void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,