diff mbox

[RFC,12/14] bbvec: Detect mode changes after uncached_cpsr update

Message ID 1438793483-12721-13-git-send-email-cov@codeaurora.org
State New
Headers show

Commit Message

Christopher Covington Aug. 5, 2015, 4:51 p.m. UTC 
The previous code checked for the mode change before the new mode was
written to env->uncached_cpsr, which unfortunately made the bbvec output
look reasonable for small tests.

Written by Aaron Lindsay.

Signed-off-by: Christopher Covington <cov@codeaurora.org>
---
 target-arm/helper.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
diff mbox

Patch

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 297eb7c..ae0a4ac 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -4281,6 +4281,9 @@  void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
     }
     mask &= ~CACHED_CPSR_BITS;
     env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
+#ifdef CONFIG_BBVEC
+    context_check_mode(env);
+#endif
 }
 
 #ifdef CONFIG_BBVEC
@@ -4540,9 +4543,6 @@  void switch_mode(CPUARMState *env, int mode)
         return;
 
         update_instruction_count(env);
-#ifdef CONFIG_BBVEC
-        context_check_mode(env);
-#endif
 
     if (old_mode == ARM_CPU_MODE_FIQ) {
         memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));