Message ID | 03d4d3a5c54263f194e72047906b61affba824c1.1438785025.git.marcel.ziswiler@toradex.com |
---|---|
State | Accepted |
Delegated to: | Tom Warren |
Headers | show |
On Wed, 2015-08-05 at 15:23 +0000, Tom Warren wrote: > Do you mind if I just roll this into my pllinfo patch when I apply it > to u-boot-tegra/master and send the PR? I'll be sure to credit your > work! Fine with me and no need for any further credits. Thanks Tom. BTW: We are currently planning our ELCE trip to Dublin. Will any of you NVIDIA open-source maintainers make it there as well (e.g. to the U -Boot Summit)?
On 08/05/2015 10:13 AM, Tom Warren wrote: > > >> -----Original Message----- >> From: Marcel Ziswiler [mailto:marcel.ziswiler@toradex.com] >> Sent: Wednesday, August 05, 2015 8:33 AM >> To: u-boot@lists.denx.de; Tom Warren >> Cc: sjg@chromium.org; trini@konsulko.com; tomcwarren3959@gmail.com; >> Thierry Reding; albert.u.boot@aribaud.net; Stephen Warren; >> yamada.m@jp.panasonic.com >> Subject: Re: [PATCH] tegra: pll: fix pllx cpcon in pllinfo table for t20/t30 >> >> On Wed, 2015-08-05 at 15:23 +0000, Tom Warren wrote: >> >>> Do you mind if I just roll this into my pllinfo patch when I apply it >>> to u-boot-tegra/master and send the PR? I'll be sure to credit your >>> work! >> >> Fine with me and no need for any further credits. Thanks Tom. >> >> BTW: We are currently planning our ELCE trip to Dublin. Will any of you NVIDIA >> open-source maintainers make it there as well (e.g. to the U -Boot Summit)? > > I won't be able to make it - maybe Stephen? Not this time around, no.
diff --git a/arch/arm/mach-tegra/tegra20/clock.c b/arch/arm/mach-tegra/tegra20/clock.c index df9f412..dea459b 100644 --- a/arch/arm/mach-tegra/tegra20/clock.c +++ b/arch/arm/mach-tegra/tegra20/clock.c @@ -379,7 +379,7 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */ { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x0F, - .lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */ + .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */ { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0, .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, diff --git a/arch/arm/mach-tegra/tegra30/clock.c b/arch/arm/mach-tegra/tegra30/clock.c index 4267bb2..3ce508b 100644 --- a/arch/arm/mach-tegra/tegra30/clock.c +++ b/arch/arm/mach-tegra/tegra30/clock.c @@ -428,7 +428,7 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */ { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F, - .lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */ + .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */ { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0, .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,