| Message ID | 1438578498-32254-6-git-send-email-architt@codeaurora.org |
|---|---|
| State | Superseded |
| Headers | show |
On Mon, Aug 03, 2015 at 10:38:18AM +0530, Archit Taneja wrote: > Enable the NAND controller node on the AP148 platform. Provide pinmux > information. > > Cc: devicetree@vger.kernel.org > > Signed-off-by: Archit Taneja <architt@codeaurora.org> > --- > arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 ++++++++++++++++++++++++++++++++ > 1 file changed, 36 insertions(+) > > diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts > index 7f9ea50..2e88eff 100644 > --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts > +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts > @@ -30,6 +30,28 @@ > bias-none; > }; > }; > + nand_pins: nand_pins { > + mux { > + pins = "gpio34", "gpio35", "gpio36", > + "gpio37", "gpio38", "gpio39", > + "gpio40", "gpio41", "gpio42", > + "gpio43", "gpio44", "gpio45", > + "gpio46", "gpio47"; > + function = "nand"; > + drive-strength = <10>; > + bias-disable; > + }; > + pullups { > + pins = "gpio39"; > + bias-pull-up; > + }; > + hold { > + pins = "gpio40", "gpio41", "gpio42", > + "gpio43", "gpio44", "gpio45", > + "gpio46", "gpio47"; > + bias-bus-hold; Maybe split out the bias-disable into a separate set and remove that property from the mux. > + }; > + }; > }; > > gsbi@16300000 { > @@ -93,5 +115,19 @@ > sata@29000000 { > status = "ok"; > }; > + > + nand@1ac00000 { > + status = "ok"; > + > + pinctrl-0 = <&nand_pins>; > + pinctrl-names = "default"; > + > + nand-ecc-strength = <4>; > + nand-bus-width = <8>; > + }; > }; > }; > + > +&adm_dma { > + status = "ok"; > +}; > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > hosted by The Linux Foundation >
On 08/03, Archit Taneja wrote: > @@ -93,5 +115,19 @@ > sata@29000000 { > status = "ok"; > }; > + > + nand@1ac00000 { > + status = "ok"; > + > + pinctrl-0 = <&nand_pins>; > + pinctrl-names = "default"; > + > + nand-ecc-strength = <4>; > + nand-bus-width = <8>; > + }; > }; > }; > + > +&adm_dma { > + status = "ok"; > +}; I think the preference is to put the full path to the device in the dts file and then have status = "ok". So please move this into the soc node and give the correct offset, etc. like we've done for other nodes.
On 8/4/2015 1:05 AM, Andy Gross wrote: > On Mon, Aug 03, 2015 at 10:38:18AM +0530, Archit Taneja wrote: >> Enable the NAND controller node on the AP148 platform. Provide pinmux >> information. >> >> Cc: devicetree@vger.kernel.org >> >> Signed-off-by: Archit Taneja <architt@codeaurora.org> >> --- >> arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 ++++++++++++++++++++++++++++++++ >> 1 file changed, 36 insertions(+) >> >> diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts >> index 7f9ea50..2e88eff 100644 >> --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts >> +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts >> @@ -30,6 +30,28 @@ >> bias-none; >> }; >> }; >> + nand_pins: nand_pins { >> + mux { >> + pins = "gpio34", "gpio35", "gpio36", >> + "gpio37", "gpio38", "gpio39", >> + "gpio40", "gpio41", "gpio42", >> + "gpio43", "gpio44", "gpio45", >> + "gpio46", "gpio47"; >> + function = "nand"; >> + drive-strength = <10>; >> + bias-disable; >> + }; >> + pullups { >> + pins = "gpio39"; >> + bias-pull-up; >> + }; >> + hold { >> + pins = "gpio40", "gpio41", "gpio42", >> + "gpio43", "gpio44", "gpio45", >> + "gpio46", "gpio47"; >> + bias-bus-hold; > > Maybe split out the bias-disable into a separate set and remove that property > from the mux. I'll fix this. Thanks, Archit
On 8/4/2015 2:28 AM, Stephen Boyd wrote: > On 08/03, Archit Taneja wrote: >> @@ -93,5 +115,19 @@ >> sata@29000000 { >> status = "ok"; >> }; >> + >> + nand@1ac00000 { >> + status = "ok"; >> + >> + pinctrl-0 = <&nand_pins>; >> + pinctrl-names = "default"; >> + >> + nand-ecc-strength = <4>; >> + nand-bus-width = <8>; >> + }; >> }; >> }; >> + >> +&adm_dma { >> + status = "ok"; >> +}; > > I think the preference is to put the full path to the device in > the dts file and then have status = "ok". So please move this > into the soc node and give the correct offset, etc. like we've > done for other nodes. I'll do that. Archit
diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts index 7f9ea50..2e88eff 100644 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts @@ -30,6 +30,28 @@ bias-none; }; }; + nand_pins: nand_pins { + mux { + pins = "gpio34", "gpio35", "gpio36", + "gpio37", "gpio38", "gpio39", + "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", + "gpio46", "gpio47"; + function = "nand"; + drive-strength = <10>; + bias-disable; + }; + pullups { + pins = "gpio39"; + bias-pull-up; + }; + hold { + pins = "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", + "gpio46", "gpio47"; + bias-bus-hold; + }; + }; }; gsbi@16300000 { @@ -93,5 +115,19 @@ sata@29000000 { status = "ok"; }; + + nand@1ac00000 { + status = "ok"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + }; }; }; + +&adm_dma { + status = "ok"; +};
Enable the NAND controller node on the AP148 platform. Provide pinmux information. Cc: devicetree@vger.kernel.org Signed-off-by: Archit Taneja <architt@codeaurora.org> --- arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 ++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+)