diff mbox

[RFCv3,1/4] docs: dts: Added documentation for Xilinx Zynq Reset Controller bindings.

Message ID 1438305237-18497-2-git-send-email-moritz.fischer@ettus.com
State Accepted, archived
Headers show

Commit Message

Moritz Fischer July 31, 2015, 1:13 a.m. UTC 
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
---
 .../devicetree/bindings/reset/zynq-reset.txt       | 68 ++++++++++++++++++++++
 1 file changed, 68 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/zynq-reset.txt

Comments

Philipp Zabel Aug. 4, 2015, 8:09 a.m. UTC | #1 
Hi Moritz,

Am Donnerstag, den 30.07.2015, 18:13 -0700 schrieb Moritz Fischer:
> Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
> ---
>  .../devicetree/bindings/reset/zynq-reset.txt       | 68 ++++++++++++++++++++++
>  1 file changed, 68 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/reset/zynq-reset.txt
> 
> diff --git a/Documentation/devicetree/bindings/reset/zynq-reset.txt b/Documentation/devicetree/bindings/reset/zynq-reset.txt
> new file mode 100644
> index 0000000..498c037a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/zynq-reset.txt
> @@ -0,0 +1,68 @@
> +Xilinx Zynq Reset Manager
> +
> +The Zynq AP-SoC has several different resets.
> +
> +See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets.
> +
> +Required properties:
> +- compatible: "xlnx,zynq-reset"
> +- reg: SLCR offset and size taken via syscon <0x200 0x48>
> +- syscon: <&slcr>
> +  This should be a phandle to the Zynq's SLCR register.

                                                 ^ register singular?

I still think the syscon phandle property is superfluous,
but I'm fine with keeping it for consistency.
It could always be made optional later.

> +- #reset-cells: Must be 1
> +
> +The Zynq Reset Manager needs to be a childnode of the SLCR.
> +
> +Example:
> +	rstc: rstc@200 {
> +		compatible = "xlnx,zynq-reset";
> +		reg = <0x200 0x48>;
> +		#reset-cells = <1>;
> +		syscon = <&slcr>;
> +	};
> +
> +Reset outputs:
> + 0  : soft reset
> + 32 : ddr reset
> + 64 : topsw reset
> + 96 : dmac reset
> + 128: usb0 reset
> + 129: usb1 reset
> + 160: gem0 reset
> + 161: gem1 reset
> + 164: gem0 rx reset
> + 165: gem1 rx reset
> + 166: gem0 ref reset
> + 167: gem1 ref reset
> + 192: sdio0 reset
> + 193: sdio1 reset
> + 196: sdio0 ref reset
> + 197: sdio1 ref reset
> + 224: spi0 reset
> + 225: spi1 reset
> + 226: spi0 ref reset
> + 227: spi1 ref reset
> + 256: can0 reset
> + 257: can1 reset
> + 258: can0 ref reset
> + 259: can1 ref reset
> + 288: i2c0 reset
> + 289: i2c1 reset
> + 320: uart0 reset
> + 321: uart1 reset
> + 322: uart0 ref reset
> + 323: uart1 ref reset
> + 352: gpio reset
> + 384: lqspi reset
> + 385: qspi ref reset
> + 416: smc reset
> + 417: smc ref reset
> + 448: ocm reset
> + 512: fpga0 out reset
> + 513: fpga1 out reset
> + 514: fpga2 out reset
> + 515: fpga3 out reset
> + 544: a9 reset 0
> + 545: a9 reset 1
> + 552: peri reset
> +

regards
Philipp

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Michal Simek Aug. 4, 2015, 8:18 a.m. UTC | #2 
On 08/04/2015 10:09 AM, Philipp Zabel wrote:
> Hi Moritz,
> 
> Am Donnerstag, den 30.07.2015, 18:13 -0700 schrieb Moritz Fischer:
>> Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
>> ---
>>  .../devicetree/bindings/reset/zynq-reset.txt       | 68 ++++++++++++++++++++++
>>  1 file changed, 68 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/reset/zynq-reset.txt
>>
>> diff --git a/Documentation/devicetree/bindings/reset/zynq-reset.txt b/Documentation/devicetree/bindings/reset/zynq-reset.txt
>> new file mode 100644
>> index 0000000..498c037a
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/reset/zynq-reset.txt
>> @@ -0,0 +1,68 @@
>> +Xilinx Zynq Reset Manager
>> +
>> +The Zynq AP-SoC has several different resets.
>> +
>> +See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets.
>> +
>> +Required properties:
>> +- compatible: "xlnx,zynq-reset"
>> +- reg: SLCR offset and size taken via syscon <0x200 0x48>
>> +- syscon: <&slcr>
>> +  This should be a phandle to the Zynq's SLCR register.
> 
>                                                  ^ register singular?
> 
> I still think the syscon phandle property is superfluous,
> but I'm fine with keeping it for consistency.
> It could always be made optional later.

Great.

Philipp: I expect you want to take at least 1/4 and 3/4 via your tree.
I am fine if you also want to add 2/4 and 4/4 via your tree.
If you think that they should go via arm-soc please let me know and I
will add them to the queue.

Thanks,
Michal
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Moritz Fischer Aug. 4, 2015, 3:05 p.m. UTC | #3 
Hi Philip,

On Tue, Aug 4, 2015 at 1:09 AM, Philipp Zabel <p.zabel@pengutronix.de> wrote:
> Hi Moritz,
>
> Am Donnerstag, den 30.07.2015, 18:13 -0700 schrieb Moritz Fischer:
>> Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
>> ---
>>  .../devicetree/bindings/reset/zynq-reset.txt       | 68 ++++++++++++++++++++++
>>  1 file changed, 68 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/reset/zynq-reset.txt
>>
>> diff --git a/Documentation/devicetree/bindings/reset/zynq-reset.txt b/Documentation/devicetree/bindings/reset/zynq-reset.txt
>> new file mode 100644
>> index 0000000..498c037a
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/reset/zynq-reset.txt
>> @@ -0,0 +1,68 @@
>> +Xilinx Zynq Reset Manager
>> +
>> +The Zynq AP-SoC has several different resets.
>> +
>> +See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets.
>> +
>> +Required properties:
>> +- compatible: "xlnx,zynq-reset"
>> +- reg: SLCR offset and size taken via syscon <0x200 0x48>
>> +- syscon: <&slcr>
>> +  This should be a phandle to the Zynq's SLCR register.
>
>                                                  ^ register singular?
Do you want me to resend the entire set, or are you cool with just git
amending the 's' for registers?

> I still think the syscon phandle property is superfluous,
> but I'm fine with keeping it for consistency.

Thanks.
> It could always be made optional later.
>
>> +- #reset-cells: Must be 1
>> +
>> +The Zynq Reset Manager needs to be a childnode of the SLCR.
>> +
>> +Example:
>> +     rstc: rstc@200 {
>> +             compatible = "xlnx,zynq-reset";
>> +             reg = <0x200 0x48>;
>> +             #reset-cells = <1>;
>> +             syscon = <&slcr>;
>> +     };
>> +
>> +Reset outputs:
>> + 0  : soft reset
>> + 32 : ddr reset
>> + 64 : topsw reset
>> + 96 : dmac reset
>> + 128: usb0 reset
>> + 129: usb1 reset
>> + 160: gem0 reset
>> + 161: gem1 reset
>> + 164: gem0 rx reset
>> + 165: gem1 rx reset
>> + 166: gem0 ref reset
>> + 167: gem1 ref reset
>> + 192: sdio0 reset
>> + 193: sdio1 reset
>> + 196: sdio0 ref reset
>> + 197: sdio1 ref reset
>> + 224: spi0 reset
>> + 225: spi1 reset
>> + 226: spi0 ref reset
>> + 227: spi1 ref reset
>> + 256: can0 reset
>> + 257: can1 reset
>> + 258: can0 ref reset
>> + 259: can1 ref reset
>> + 288: i2c0 reset
>> + 289: i2c1 reset
>> + 320: uart0 reset
>> + 321: uart1 reset
>> + 322: uart0 ref reset
>> + 323: uart1 ref reset
>> + 352: gpio reset
>> + 384: lqspi reset
>> + 385: qspi ref reset
>> + 416: smc reset
>> + 417: smc ref reset
>> + 448: ocm reset
>> + 512: fpga0 out reset
>> + 513: fpga1 out reset
>> + 514: fpga2 out reset
>> + 515: fpga3 out reset
>> + 544: a9 reset 0
>> + 545: a9 reset 1
>> + 552: peri reset
>> +
>
> regards
> Philipp
>

Cheers,

Moritz
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Philipp Zabel Aug. 4, 2015, 3:10 p.m. UTC | #4 
Hi Moritz,

Am Dienstag, den 04.08.2015, 08:05 -0700 schrieb Moritz Fischer:
> Hi Philip,
> 
> On Tue, Aug 4, 2015 at 1:09 AM, Philipp Zabel <p.zabel@pengutronix.de> wrote:
> > Hi Moritz,
> >
> > Am Donnerstag, den 30.07.2015, 18:13 -0700 schrieb Moritz Fischer:
[...]
> >> +Required properties:
> >> +- compatible: "xlnx,zynq-reset"
> >> +- reg: SLCR offset and size taken via syscon <0x200 0x48>
> >> +- syscon: <&slcr>
> >> +  This should be a phandle to the Zynq's SLCR register.
> >
> >                                                  ^ register singular?
> Do you want me to resend the entire set, or are you cool with just git
> amending the 's' for registers?

Amended and applied, thanks.

regards
Philipp

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Moritz Fischer Aug. 5, 2015, 7:43 p.m. UTC | #5 
Michal,

On Tue, Aug 4, 2015 at 8:10 AM, Philipp Zabel <p.zabel@pengutronix.de> wrote:
> Hi Moritz,
>
> Am Dienstag, den 04.08.2015, 08:05 -0700 schrieb Moritz Fischer:
>> Hi Philip,
>>
>> On Tue, Aug 4, 2015 at 1:09 AM, Philipp Zabel <p.zabel@pengutronix.de> wrote:
>> > Hi Moritz,
>> >
>> > Am Donnerstag, den 30.07.2015, 18:13 -0700 schrieb Moritz Fischer:
> [...]
>> >> +Required properties:
>> >> +- compatible: "xlnx,zynq-reset"
>> >> +- reg: SLCR offset and size taken via syscon <0x200 0x48>
>> >> +- syscon: <&slcr>
>> >> +  This should be a phandle to the Zynq's SLCR register.
>> >
>> >                                                  ^ register singular?
>> Do you want me to resend the entire set, or are you cool with just git
>> amending the 's' for registers?
>
> Amended and applied, thanks.

Will you take 4/4 and 2/4 via your tree?
>
> regards
> Philipp
>

Thanks,

Moritz
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Michal Simek Aug. 6, 2015, 4:54 a.m. UTC | #6 
On 08/05/2015 09:43 PM, Moritz Fischer wrote:
> Michal,
> 
> On Tue, Aug 4, 2015 at 8:10 AM, Philipp Zabel <p.zabel@pengutronix.de> wrote:
>> Hi Moritz,
>>
>> Am Dienstag, den 04.08.2015, 08:05 -0700 schrieb Moritz Fischer:
>>> Hi Philip,
>>>
>>> On Tue, Aug 4, 2015 at 1:09 AM, Philipp Zabel <p.zabel@pengutronix.de> wrote:
>>>> Hi Moritz,
>>>>
>>>> Am Donnerstag, den 30.07.2015, 18:13 -0700 schrieb Moritz Fischer:
>> [...]
>>>>> +Required properties:
>>>>> +- compatible: "xlnx,zynq-reset"
>>>>> +- reg: SLCR offset and size taken via syscon <0x200 0x48>
>>>>> +- syscon: <&slcr>
>>>>> +  This should be a phandle to the Zynq's SLCR register.
>>>>
>>>>                                                  ^ register singular?
>>> Do you want me to resend the entire set, or are you cool with just git
>>> amending the 's' for registers?
>>
>> Amended and applied, thanks.
> 
> Will you take 4/4 and 2/4 via your tree?

Applied to zynq/dt and zynq/soc.

Thanks,
Michal

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diff mbox

Patch

diff --git a/Documentation/devicetree/bindings/reset/zynq-reset.txt b/Documentation/devicetree/bindings/reset/zynq-reset.txt
new file mode 100644
index 0000000..498c037a
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/zynq-reset.txt
@@ -0,0 +1,68 @@ 
+Xilinx Zynq Reset Manager
+
+The Zynq AP-SoC has several different resets.
+
+See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets.
+
+Required properties:
+- compatible: "xlnx,zynq-reset"
+- reg: SLCR offset and size taken via syscon <0x200 0x48>
+- syscon: <&slcr>
+  This should be a phandle to the Zynq's SLCR register.
+- #reset-cells: Must be 1
+
+The Zynq Reset Manager needs to be a childnode of the SLCR.
+
+Example:
+	rstc: rstc@200 {
+		compatible = "xlnx,zynq-reset";
+		reg = <0x200 0x48>;
+		#reset-cells = <1>;
+		syscon = <&slcr>;
+	};
+
+Reset outputs:
+ 0  : soft reset
+ 32 : ddr reset
+ 64 : topsw reset
+ 96 : dmac reset
+ 128: usb0 reset
+ 129: usb1 reset
+ 160: gem0 reset
+ 161: gem1 reset
+ 164: gem0 rx reset
+ 165: gem1 rx reset
+ 166: gem0 ref reset
+ 167: gem1 ref reset
+ 192: sdio0 reset
+ 193: sdio1 reset
+ 196: sdio0 ref reset
+ 197: sdio1 ref reset
+ 224: spi0 reset
+ 225: spi1 reset
+ 226: spi0 ref reset
+ 227: spi1 ref reset
+ 256: can0 reset
+ 257: can1 reset
+ 258: can0 ref reset
+ 259: can1 ref reset
+ 288: i2c0 reset
+ 289: i2c1 reset
+ 320: uart0 reset
+ 321: uart1 reset
+ 322: uart0 ref reset
+ 323: uart1 ref reset
+ 352: gpio reset
+ 384: lqspi reset
+ 385: qspi ref reset
+ 416: smc reset
+ 417: smc ref reset
+ 448: ocm reset
+ 512: fpga0 out reset
+ 513: fpga1 out reset
+ 514: fpga2 out reset
+ 515: fpga3 out reset
+ 544: a9 reset 0
+ 545: a9 reset 1
+ 552: peri reset
+