diff mbox

[U-Boot,U-Boot,v2,08/10] dma: ti-edma3: Add helper function to support edma3 transfer

Message ID 1438234483-3738-9-git-send-email-vigneshr@ti.com
State Superseded
Delegated to: Jagannadha Sutradharudu Teki
Headers show

Commit Message

Raghavendra, Vignesh July 30, 2015, 5:34 a.m. UTC
Signed-off-by: Vignesh R <vigneshr@ti.com>
---
 arch/arm/include/asm/ti-common/ti-edma3.h |  2 +
 drivers/dma/ti-edma3.c                    | 78 +++++++++++++++++++++++++++++++
 2 files changed, 80 insertions(+)

Comments

Jagan Teki Aug. 13, 2015, 5:50 p.m. UTC | #1
On 30 July 2015 at 11:04, Vignesh R <vigneshr@ti.com> wrote:
> Signed-off-by: Vignesh R <vigneshr@ti.com>

Reviewed-by: Jagan Teki <jteki@openedev.com>

> ---
>  arch/arm/include/asm/ti-common/ti-edma3.h |  2 +
>  drivers/dma/ti-edma3.c                    | 78 +++++++++++++++++++++++++++++++
>  2 files changed, 80 insertions(+)
>
> diff --git a/arch/arm/include/asm/ti-common/ti-edma3.h b/arch/arm/include/asm/ti-common/ti-edma3.h
> index 5adc1dac0e65..6a7a321c1bdf 100644
> --- a/arch/arm/include/asm/ti-common/ti-edma3.h
> +++ b/arch/arm/include/asm/ti-common/ti-edma3.h
> @@ -117,5 +117,7 @@ void edma3_set_src_addr(u32 base, int slot, u32 src);
>  void edma3_set_transfer_params(u32 base, int slot, int acnt,
>                                int bcnt, int ccnt, u16 bcnt_rld,
>                                enum edma3_sync_dimension sync_mode);
> +void edma3_transfer(unsigned long edma3_base_addr, unsigned int
> +               edma_slot_num, void *dst, void *src, size_t len);
>
>  #endif
> diff --git a/drivers/dma/ti-edma3.c b/drivers/dma/ti-edma3.c
> index 8184ded9fa81..d6a427f2e21d 100644
> --- a/drivers/dma/ti-edma3.c
> +++ b/drivers/dma/ti-edma3.c
> @@ -382,3 +382,81 @@ void qedma3_stop(u32 base, struct edma3_channel_config *cfg)
>         /* Clear the channel map */
>         __raw_writel(0, base + EDMA3_QCHMAP(cfg->chnum));
>  }
> +
> +void edma3_transfer(unsigned long edma3_base_addr, unsigned int
> +                   edma_slot_num, void *dst, void *src, size_t len)
> +{
> +       struct edma3_slot_config        slot;
> +       struct edma3_channel_config     edma_channel;
> +       int                             b_cnt_value = 1;
> +       int                             rem_bytes  = 0;
> +       int                             a_cnt_value = len;
> +       unsigned int                    addr = (unsigned int) (dst);
> +       unsigned int                    max_acnt  = 0x7FFFU;
> +
> +       if (len > max_acnt) {
> +               b_cnt_value = (len / max_acnt);
> +               rem_bytes  = (len % max_acnt);
> +               a_cnt_value = max_acnt;
> +       }
> +
> +       slot.opt        = 0;
> +       slot.src        = ((unsigned int) src);
> +       slot.acnt       = a_cnt_value;
> +       slot.bcnt       = b_cnt_value;
> +       slot.ccnt       = 1;
> +       slot.src_bidx   = a_cnt_value;
> +       slot.dst_bidx   = a_cnt_value;
> +       slot.src_cidx   = 0;
> +       slot.dst_cidx   = 0;
> +       slot.link       = EDMA3_PARSET_NULL_LINK;
> +       slot.bcntrld    = 0;
> +       slot.opt        = EDMA3_SLOPT_TRANS_COMP_INT_ENB |
> +                         EDMA3_SLOPT_COMP_CODE(0) |
> +                         EDMA3_SLOPT_STATIC | EDMA3_SLOPT_AB_SYNC;
> +
> +       edma3_slot_configure(edma3_base_addr, edma_slot_num, &slot);
> +       edma_channel.slot = edma_slot_num;
> +       edma_channel.chnum = 0;
> +       edma_channel.complete_code = 0;
> +        /* set event trigger to dst update */
> +       edma_channel.trigger_slot_word = EDMA3_TWORD(dst);
> +
> +       qedma3_start(edma3_base_addr, &edma_channel);
> +       edma3_set_dest_addr(edma3_base_addr, edma_channel.slot, addr);
> +
> +       while (edma3_check_for_transfer(edma3_base_addr, &edma_channel))
> +               ;

Can't we do with proper timeout, status from reg or some thing.

> +       qedma3_stop(edma3_base_addr, &edma_channel);
> +
> +       if (rem_bytes != 0) {
> +               slot.opt        = 0;
> +               slot.src        =
> +                       (b_cnt_value * max_acnt) + ((unsigned int) src);
> +               slot.acnt       = rem_bytes;
> +               slot.bcnt       = 1;
> +               slot.ccnt       = 1;
> +               slot.src_bidx   = rem_bytes;
> +               slot.dst_bidx   = rem_bytes;
> +               slot.src_cidx   = 0;
> +               slot.dst_cidx   = 0;
> +               slot.link       = EDMA3_PARSET_NULL_LINK;
> +               slot.bcntrld    = 0;
> +               slot.opt        = EDMA3_SLOPT_TRANS_COMP_INT_ENB |
> +                                 EDMA3_SLOPT_COMP_CODE(0) |
> +                                 EDMA3_SLOPT_STATIC | EDMA3_SLOPT_AB_SYNC;
> +               edma3_slot_configure(edma3_base_addr, edma_slot_num, &slot);
> +               edma_channel.slot = edma_slot_num;
> +               edma_channel.chnum = 0;
> +               edma_channel.complete_code = 0;
> +               /* set event trigger to dst update */
> +               edma_channel.trigger_slot_word = EDMA3_TWORD(dst);
> +
> +               qedma3_start(edma3_base_addr, &edma_channel);
> +               edma3_set_dest_addr(edma3_base_addr, edma_channel.slot, addr +
> +                                   (max_acnt * b_cnt_value));
> +               while (edma3_check_for_transfer(edma3_base_addr, &edma_channel))
> +                       ;
> +               qedma3_stop(edma3_base_addr, &edma_channel);
> +       }
> +}
> --
> 2.5.0
>

thanks!
diff mbox

Patch

diff --git a/arch/arm/include/asm/ti-common/ti-edma3.h b/arch/arm/include/asm/ti-common/ti-edma3.h
index 5adc1dac0e65..6a7a321c1bdf 100644
--- a/arch/arm/include/asm/ti-common/ti-edma3.h
+++ b/arch/arm/include/asm/ti-common/ti-edma3.h
@@ -117,5 +117,7 @@  void edma3_set_src_addr(u32 base, int slot, u32 src);
 void edma3_set_transfer_params(u32 base, int slot, int acnt,
 			       int bcnt, int ccnt, u16 bcnt_rld,
 			       enum edma3_sync_dimension sync_mode);
+void edma3_transfer(unsigned long edma3_base_addr, unsigned int
+		edma_slot_num, void *dst, void *src, size_t len);
 
 #endif
diff --git a/drivers/dma/ti-edma3.c b/drivers/dma/ti-edma3.c
index 8184ded9fa81..d6a427f2e21d 100644
--- a/drivers/dma/ti-edma3.c
+++ b/drivers/dma/ti-edma3.c
@@ -382,3 +382,81 @@  void qedma3_stop(u32 base, struct edma3_channel_config *cfg)
 	/* Clear the channel map */
 	__raw_writel(0, base + EDMA3_QCHMAP(cfg->chnum));
 }
+
+void edma3_transfer(unsigned long edma3_base_addr, unsigned int
+		    edma_slot_num, void *dst, void *src, size_t len)
+{
+	struct edma3_slot_config        slot;
+	struct edma3_channel_config     edma_channel;
+	int                             b_cnt_value = 1;
+	int                             rem_bytes  = 0;
+	int                             a_cnt_value = len;
+	unsigned int                    addr = (unsigned int) (dst);
+	unsigned int                    max_acnt  = 0x7FFFU;
+
+	if (len > max_acnt) {
+		b_cnt_value = (len / max_acnt);
+		rem_bytes  = (len % max_acnt);
+		a_cnt_value = max_acnt;
+	}
+
+	slot.opt        = 0;
+	slot.src        = ((unsigned int) src);
+	slot.acnt       = a_cnt_value;
+	slot.bcnt       = b_cnt_value;
+	slot.ccnt       = 1;
+	slot.src_bidx   = a_cnt_value;
+	slot.dst_bidx   = a_cnt_value;
+	slot.src_cidx   = 0;
+	slot.dst_cidx   = 0;
+	slot.link       = EDMA3_PARSET_NULL_LINK;
+	slot.bcntrld    = 0;
+	slot.opt        = EDMA3_SLOPT_TRANS_COMP_INT_ENB |
+			  EDMA3_SLOPT_COMP_CODE(0) |
+			  EDMA3_SLOPT_STATIC | EDMA3_SLOPT_AB_SYNC;
+
+	edma3_slot_configure(edma3_base_addr, edma_slot_num, &slot);
+	edma_channel.slot = edma_slot_num;
+	edma_channel.chnum = 0;
+	edma_channel.complete_code = 0;
+	 /* set event trigger to dst update */
+	edma_channel.trigger_slot_word = EDMA3_TWORD(dst);
+
+	qedma3_start(edma3_base_addr, &edma_channel);
+	edma3_set_dest_addr(edma3_base_addr, edma_channel.slot, addr);
+
+	while (edma3_check_for_transfer(edma3_base_addr, &edma_channel))
+		;
+	qedma3_stop(edma3_base_addr, &edma_channel);
+
+	if (rem_bytes != 0) {
+		slot.opt        = 0;
+		slot.src        =
+			(b_cnt_value * max_acnt) + ((unsigned int) src);
+		slot.acnt       = rem_bytes;
+		slot.bcnt       = 1;
+		slot.ccnt       = 1;
+		slot.src_bidx   = rem_bytes;
+		slot.dst_bidx   = rem_bytes;
+		slot.src_cidx   = 0;
+		slot.dst_cidx   = 0;
+		slot.link       = EDMA3_PARSET_NULL_LINK;
+		slot.bcntrld    = 0;
+		slot.opt        = EDMA3_SLOPT_TRANS_COMP_INT_ENB |
+				  EDMA3_SLOPT_COMP_CODE(0) |
+				  EDMA3_SLOPT_STATIC | EDMA3_SLOPT_AB_SYNC;
+		edma3_slot_configure(edma3_base_addr, edma_slot_num, &slot);
+		edma_channel.slot = edma_slot_num;
+		edma_channel.chnum = 0;
+		edma_channel.complete_code = 0;
+		/* set event trigger to dst update */
+		edma_channel.trigger_slot_word = EDMA3_TWORD(dst);
+
+		qedma3_start(edma3_base_addr, &edma_channel);
+		edma3_set_dest_addr(edma3_base_addr, edma_channel.slot, addr +
+				    (max_acnt * b_cnt_value));
+		while (edma3_check_for_transfer(edma3_base_addr, &edma_channel))
+			;
+		qedma3_stop(edma3_base_addr, &edma_channel);
+	}
+}