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[U-Boot,U-Boot,v2,05/10] ARM: OMAP5: Add functions to enable and disable EDMA3 clocks

Message ID 1438234483-3738-6-git-send-email-vigneshr@ti.com
State Superseded
Delegated to: Jagannadha Sutradharudu Teki
Headers show

Commit Message

Raghavendra, Vignesh July 30, 2015, 5:34 a.m. UTC
Adds functions to enable and disable edma3 clocks which can be invoked
by drivers using edma3 to control the clocks.

Signed-off-by: Vignesh R <vigneshr@ti.com>
---
 arch/arm/cpu/armv7/omap5/hw_data.c   | 41 ++++++++++++++++++++++++++++++++++++
 arch/arm/cpu/armv7/omap5/prcm-regs.c |  4 ++++
 arch/arm/include/asm/omap_common.h   |  9 ++++++++
 3 files changed, 54 insertions(+)

Comments

Tom Rini Aug. 13, 2015, 6:26 p.m. UTC | #1
On Thu, Jul 30, 2015 at 11:04:38AM +0530, Vignesh R wrote:

> Adds functions to enable and disable edma3 clocks which can be invoked
> by drivers using edma3 to control the clocks.
> 
> Signed-off-by: Vignesh R <vigneshr@ti.com>
[snip]
> diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
> index 87cdaad1d60f..3dbe9c53d202 100644
> --- a/arch/arm/include/asm/omap_common.h
> +++ b/arch/arm/include/asm/omap_common.h
> @@ -349,6 +349,10 @@ struct prcm_regs {
>  	/* IPU */
>  	u32 cm_ipu_clkstctrl;
>  	u32 cm_ipu_i2c5_clkctrl;
> +
> +	/*l3main1 edma*/
> +	u32 cm_l3main1_tptc1_clkctrl;
> +	u32 cm_l3main1_tptc2_clkctrl;
>  };
>  
>  struct omap_sys_ctrl_regs {
> @@ -598,6 +602,11 @@ void recalibrate_iodelay(void);
>  
>  void omap_smc1(u32 service, u32 val);
>  
> +#ifdef CONFIG_TI_EDMA3
> +void enable_edma3_clocks(void);
> +void disable_edma3_clocks(void);
> +#endif

No #ifdef/#endif in headers please.
diff mbox

Patch

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 3a723cace71a..33f92b7e225d 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -565,6 +565,47 @@  void enable_basic_uboot_clocks(void)
 			 1);
 }
 
+#ifdef CONFIG_TI_EDMA3
+void enable_edma3_clocks(void)
+{
+	u32 const clk_domains_edma3[] = {
+		0
+	};
+
+	u32 const clk_modules_hw_auto_edma3[] = {
+		(*prcm)->cm_l3main1_tptc1_clkctrl,
+		(*prcm)->cm_l3main1_tptc2_clkctrl,
+		0
+	};
+
+	u32 const clk_modules_explicit_en_edma3[] = {
+		0
+	};
+
+	do_enable_clocks(clk_domains_edma3,
+			 clk_modules_hw_auto_edma3,
+			 clk_modules_explicit_en_edma3,
+			 1);
+}
+
+void disable_edma3_clocks(void)
+{
+	u32 const clk_domains_edma3[] = {
+		0
+	};
+
+	u32 const clk_modules_disable_edma3[] = {
+		(*prcm)->cm_l3main1_tptc1_clkctrl,
+		(*prcm)->cm_l3main1_tptc2_clkctrl,
+		0
+	};
+
+	do_disable_clocks(clk_domains_edma3,
+			  clk_modules_disable_edma3,
+			  1);
+}
+#endif
+
 const struct ctrl_ioregs ioregs_omap5430 = {
 	.ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
 	.ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index cd51fe7678be..d01ce88306ee 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -989,4 +989,8 @@  struct prcm_regs const dra7xx_prcm = {
 
 	.prm_abbldo_mpu_setup			= 0x4AE07DDC,
 	.prm_abbldo_mpu_ctrl			= 0x4AE07DE0,
+
+	/*l3main1 edma*/
+	.cm_l3main1_tptc1_clkctrl               = 0x4a008778,
+	.cm_l3main1_tptc2_clkctrl               = 0x4a008780,
 };
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 87cdaad1d60f..3dbe9c53d202 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -349,6 +349,10 @@  struct prcm_regs {
 	/* IPU */
 	u32 cm_ipu_clkstctrl;
 	u32 cm_ipu_i2c5_clkctrl;
+
+	/*l3main1 edma*/
+	u32 cm_l3main1_tptc1_clkctrl;
+	u32 cm_l3main1_tptc2_clkctrl;
 };
 
 struct omap_sys_ctrl_regs {
@@ -598,6 +602,11 @@  void recalibrate_iodelay(void);
 
 void omap_smc1(u32 service, u32 val);
 
+#ifdef CONFIG_TI_EDMA3
+void enable_edma3_clocks(void);
+void disable_edma3_clocks(void);
+#endif
+
 /* ABB */
 #define OMAP_ABB_NOMINAL_OPP		0
 #define OMAP_ABB_FAST_OPP		1