From patchwork Tue Apr 13 23:13:49 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 50181 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 7D38EB7D1D for ; Thu, 15 Apr 2010 07:05:24 +1000 (EST) Received: from localhost ([127.0.0.1]:37764 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1O29kl-0001OE-MX for incoming@patchwork.ozlabs.org; Wed, 14 Apr 2010 17:04:07 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1O29XO-0004jx-Ue for qemu-devel@nongnu.org; Wed, 14 Apr 2010 16:50:19 -0400 Received: from [140.186.70.92] (port=35369 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1O29XE-0004W1-BK for qemu-devel@nongnu.org; Wed, 14 Apr 2010 16:50:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1O29XB-0001O4-9Q for qemu-devel@nongnu.org; Wed, 14 Apr 2010 16:50:06 -0400 Received: from are.twiddle.net ([75.149.56.221]:41943) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1O29XA-0001Nr-W5 for qemu-devel@nongnu.org; Wed, 14 Apr 2010 16:50:05 -0400 Received: by are.twiddle.net (Postfix, from userid 5000) id 6B420EC3; Wed, 14 Apr 2010 13:50:04 -0700 (PDT) Message-Id: <0e0f0ea69509d0ab8b42f605277334c9be0e8501.1271277329.git.rth@twiddle.net> In-Reply-To: References: From: Richard Henderson Date: Tue, 13 Apr 2010 16:13:49 -0700 To: qemu-devel@nongnu.org X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 04/21] tcg-i386: Tidy ext8s and ext16s operations. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Define OPC_MOVSBL and OPC_MOVSWL. Factor opcode emission to separate functions. Don't restrict the input register to the low 4 "q" registers; emit shifts instead if needed. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c | 49 +++++++++++++++++++++++++++++++++++++------------ 1 files changed, 37 insertions(+), 12 deletions(-) diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c index 2cc1191..75b9915 100644 --- a/tcg/i386/tcg-target.c +++ b/tcg/i386/tcg-target.c @@ -165,6 +165,8 @@ static inline int tcg_target_const_match(tcg_target_long val, #define OPC_MOVZBL (0xb6 | P_EXT) #define OPC_MOVZWL (0xb7 | P_EXT) +#define OPC_MOVSBL (0xbe | P_EXT) +#define OPC_MOVSWL (0xbf | P_EXT) #define ARITH_ADD 0 #define ARITH_OR 1 @@ -306,12 +308,37 @@ static void tcg_out_ext8u(TCGContext *s, int dest, int src) tcg_out_modrm(s, OPC_MOVZBL, dest, src); } +static void tcg_out_ext8s(TCGContext *s, int dest, int src) +{ + if (src >= 4) { + tcg_out_mov(s, dest, src); + if (dest >= 4) { + /* shl $24, dest */ + tcg_out_modrm(s, 0xc1, SHIFT_SHL, dest); + tcg_out8(s, 24); + /* sar $24, dest */ + tcg_out_modrm(s, 0xc1, SHIFT_SAR, dest); + tcg_out8(s, 24); + return; + } + src = dest; + } + /* movsbl */ + tcg_out_modrm(s, OPC_MOVSBL, dest, src); +} + static inline void tcg_out_ext16u(TCGContext *s, int dest, int src) { /* movzwl */ tcg_out_modrm(s, OPC_MOVZWL, dest, src); } +static inline void tcg_out_ext16s(TCGContext *s, int dest, int src) +{ + /* movswl */ + tcg_out_modrm(s, OPC_MOVSWL, dest, src); +} + static inline void tgen_arithi(TCGContext *s, int c, int r0, int32_t val, int cf) { if (!cf && ((c == ARITH_ADD && val == 1) || (c == ARITH_SUB && val == -1))) { @@ -659,12 +686,10 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, switch(opc) { case 0 | 4: - /* movsbl */ - tcg_out_modrm(s, 0xbe | P_EXT, data_reg, TCG_REG_EAX); + tcg_out_ext8s(s, data_reg, TCG_REG_EAX); break; case 1 | 4: - /* movswl */ - tcg_out_modrm(s, 0xbf | P_EXT, data_reg, TCG_REG_EAX); + tcg_out_ext16s(s, data_reg, TCG_REG_EAX); break; case 0: tcg_out_ext8u(s, data_reg, TCG_REG_EAX); @@ -714,7 +739,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, break; case 0 | 4: /* movsbl */ - tcg_out_modrm_offset(s, 0xbe | P_EXT, data_reg, r0, GUEST_BASE); + tcg_out_modrm_offset(s, OPC_MOVSBL, data_reg, r0, GUEST_BASE); break; case 1: /* movzwl */ @@ -728,7 +753,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, break; case 1 | 4: /* movswl */ - tcg_out_modrm_offset(s, 0xbf | P_EXT, data_reg, r0, GUEST_BASE); + tcg_out_modrm_offset(s, OPC_MOVSWL, data_reg, r0, GUEST_BASE); if (bswap) { /* rolw $8, data_reg */ tcg_out8(s, 0x66); @@ -736,7 +761,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, tcg_out8(s, 8); /* movswl data_reg, data_reg */ - tcg_out_modrm(s, 0xbf | P_EXT, data_reg, data_reg); + tcg_out_modrm(s, OPC_MOVSWL, data_reg, data_reg); } break; case 2: @@ -1042,7 +1067,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_ld8s_i32: /* movsbl */ - tcg_out_modrm_offset(s, 0xbe | P_EXT, args[0], args[1], args[2]); + tcg_out_modrm_offset(s, OPC_MOVSBL, args[0], args[1], args[2]); break; case INDEX_op_ld16u_i32: /* movzwl */ @@ -1050,7 +1075,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_ld16s_i32: /* movswl */ - tcg_out_modrm_offset(s, 0xbf | P_EXT, args[0], args[1], args[2]); + tcg_out_modrm_offset(s, OPC_MOVSWL, args[0], args[1], args[2]); break; case INDEX_op_ld_i32: /* movl */ @@ -1187,10 +1212,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_ext8s_i32: - tcg_out_modrm(s, 0xbe | P_EXT, args[0], args[1]); + tcg_out_ext8s(s, args[0], args[1]); break; case INDEX_op_ext16s_i32: - tcg_out_modrm(s, 0xbf | P_EXT, args[0], args[1]); + tcg_out_ext16s(s, args[0], args[1]); break; case INDEX_op_ext8u_i32: tcg_out_ext8u(s, args[0], args[1]); @@ -1289,7 +1314,7 @@ static const TCGTargetOpDef x86_op_defs[] = { { INDEX_op_not_i32, { "r", "0" } }, - { INDEX_op_ext8s_i32, { "r", "q" } }, + { INDEX_op_ext8s_i32, { "r", "r" } }, { INDEX_op_ext16s_i32, { "r", "r" } }, { INDEX_op_ext8u_i32, { "r", "r" } }, { INDEX_op_ext16u_i32, { "r", "r" } },