diff mbox

Re: [PATCH] [PATCH][ARM] Fix sibcall testcases.

Message ID 55B7BFD6.2080909@arm.com
State New
Headers show

Commit Message

Alex Velenko July 28, 2015, 5:45 p.m. UTC 
Hi,

Following last patch, this patch patch prevents arm_thumb1 XPASS in
sibcall-3.c and sibcall-4.c by skipping on arm_thumb1 and arm_thumb2
respectively.
This patch also documents arm_thumb1 and arm_thumb2 effective target 
options.

Is patch ok for trunk and fsf-5?

gcc/testsuite

2015-07-28  Alex Velenko  <Alex.Velenko@arm.com>

         * gcc.dg/sibcall-3.c (dg-skip-if): Skip if arm_thumb1.
         * gcc.dg/sibcall-4.c (dg-skip-if): Likewise.

gcc/

2015-07-28  Alex Velenko  <Alex.Velenko@arm.com>

         * doc/sourcebuild.texi (arm_thumb1): Documented.
         (arm-thumb2): Likewise.
---
  gcc/doc/sourcebuild.texi         | 8 ++++++++
  gcc/testsuite/gcc.dg/sibcall-3.c | 1 +
  gcc/testsuite/gcc.dg/sibcall-4.c | 1 +
  3 files changed, 10 insertions(+)


  /* The option -foptimize-sibling-calls is the default, but serves as
diff mbox

Patch

diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index c6ef40e..ca42a09 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -1551,6 +1551,14 @@  options.  Some multilibs may be incompatible with 
these options.
  ARM Target supports @code{-mfpu=neon-fp16 -mfloat-abi=softfp} or 
compatible
  options.  Some multilibs may be incompatible with these options.

+@item arm_thumb1
+ARM target interworks with Thumb-1 - given @code{-mthumb-interwork} 
both ARM and
+Thumb code may be generated interleaved.
+
+@item arm_thumb2
+ARM target interworks with Thumb-2 - given @code{-mthumb-interwork} 
both ARM and
+Thumb code may be generated interleaved.
+
  @item arm_thumb1_ok
  ARM target generates Thumb-1 code for @code{-mthumb}.

diff --git a/gcc/testsuite/gcc.dg/sibcall-3.c 
b/gcc/testsuite/gcc.dg/sibcall-3.c
index eafe8dd..e44596e 100644
--- a/gcc/testsuite/gcc.dg/sibcall-3.c
+++ b/gcc/testsuite/gcc.dg/sibcall-3.c
@@ -8,6 +8,7 @@ 
  /* { dg-do run { xfail { { cris-*-* crisv32-*-* h8300-*-* hppa*64*-*-* 
m32r-*-* mcore-*-* mn10300-*-* msp430*-*-* nds32*-*-* xstormy16-*-* 
v850*-*-* vax-*-* xtensa*-*-* } || { arm*-*-* && { ! arm32 } } } } } */
  /* -mlongcall disables sibcall patterns.  */
  /* { dg-skip-if "" { powerpc*-*-* } { "-mlongcall" } { "" } } */
+/* { dg-skip-if "" { arm_thumb1 } } */
  /* { dg-options "-O2 -foptimize-sibling-calls" } */

  /* The option -foptimize-sibling-calls is the default, but serves as
diff --git a/gcc/testsuite/gcc.dg/sibcall-4.c 
b/gcc/testsuite/gcc.dg/sibcall-4.c
index 1e039c6..5c69490 100644
--- a/gcc/testsuite/gcc.dg/sibcall-4.c
+++ b/gcc/testsuite/gcc.dg/sibcall-4.c
@@ -8,6 +8,7 @@ 
  /* { dg-do run { xfail { { cris-*-* crisv32-*-* h8300-*-* hppa*64*-*-* 
m32r-*-* mcore-*-* mn10300-*-* msp430*-*-* nds32*-*-* xstormy16-*-* 
v850*-*-* vax-*-* xtensa*-*-* } || { arm*-*-* && { ! arm32 } } } } } */
  /* -mlongcall disables sibcall patterns.  */
  /* { dg-skip-if "" { powerpc*-*-* } { "-mlongcall" } { "" } } */
+/* { dg-skip-if "" { arm_thumb1 } } */
  /* { dg-options "-O2 -foptimize-sibling-calls" } */