diff mbox

[U-Boot,10/15] x86: dts: Fix typo in intel,irq-router.txt

Message ID 1438033652-30435-11-git-send-email-sjg@chromium.org
State Accepted
Delegated to: Simon Glass
Headers show

Commit Message

Simon Glass July 27, 2015, 9:47 p.m. UTC
Fix a small typo in this binding file.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 doc/device-tree-bindings/misc/intel,irq-router.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Bin Meng July 28, 2015, 7:48 a.m. UTC | #1
On Tue, Jul 28, 2015 at 5:47 AM, Simon Glass <sjg@chromium.org> wrote:
> Fix a small typo in this binding file.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  doc/device-tree-bindings/misc/intel,irq-router.txt | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/doc/device-tree-bindings/misc/intel,irq-router.txt b/doc/device-tree-bindings/misc/intel,irq-router.txt
> index 598b4b1..e4d8ead 100644
> --- a/doc/device-tree-bindings/misc/intel,irq-router.txt
> +++ b/doc/device-tree-bindings/misc/intel,irq-router.txt
> @@ -17,8 +17,8 @@ Required properties :
>  - intel,pirq-link : Specifies the PIRQ link information with two cells. The
>      first cell is the register offset that controls the first PIRQ link routing.
>      The second cell is the total number of PIRQ links the router supports.
> -- intel,pirq-mask : Specifies the IRQ mask reprenting the 16 IRQs in 8259 PIC.
> -    Bit N is 1 means IRQ N is available to be routed.
> +- intel,pirq-mask : Specifies the IRQ mask representing the 16 IRQs in the
> +    8259 PIC. Bit N is 1 means IRQ N is available to be routed.
>  - intel,pirq-routing : Specifies all PCI devices' IRQ routing information,
>     encoded as 3 cells a group for a device. The first cell is the device's PCI
>     bus number, device number and function number encoding with PCI_BDF() macro.
> --

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass Aug. 2, 2015, 11:38 p.m. UTC | #2
On 28 July 2015 at 01:48, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Tue, Jul 28, 2015 at 5:47 AM, Simon Glass <sjg@chromium.org> wrote:
>> Fix a small typo in this binding file.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>>  doc/device-tree-bindings/misc/intel,irq-router.txt | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/doc/device-tree-bindings/misc/intel,irq-router.txt b/doc/device-tree-bindings/misc/intel,irq-router.txt
>> index 598b4b1..e4d8ead 100644
>> --- a/doc/device-tree-bindings/misc/intel,irq-router.txt
>> +++ b/doc/device-tree-bindings/misc/intel,irq-router.txt
>> @@ -17,8 +17,8 @@ Required properties :
>>  - intel,pirq-link : Specifies the PIRQ link information with two cells. The
>>      first cell is the register offset that controls the first PIRQ link routing.
>>      The second cell is the total number of PIRQ links the router supports.
>> -- intel,pirq-mask : Specifies the IRQ mask reprenting the 16 IRQs in 8259 PIC.
>> -    Bit N is 1 means IRQ N is available to be routed.
>> +- intel,pirq-mask : Specifies the IRQ mask representing the 16 IRQs in the
>> +    8259 PIC. Bit N is 1 means IRQ N is available to be routed.
>>  - intel,pirq-routing : Specifies all PCI devices' IRQ routing information,
>>     encoded as 3 cells a group for a device. The first cell is the device's PCI
>>     bus number, device number and function number encoding with PCI_BDF() macro.
>> --
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Applied to u-boot-x86.
diff mbox

Patch

diff --git a/doc/device-tree-bindings/misc/intel,irq-router.txt b/doc/device-tree-bindings/misc/intel,irq-router.txt
index 598b4b1..e4d8ead 100644
--- a/doc/device-tree-bindings/misc/intel,irq-router.txt
+++ b/doc/device-tree-bindings/misc/intel,irq-router.txt
@@ -17,8 +17,8 @@  Required properties :
 - intel,pirq-link : Specifies the PIRQ link information with two cells. The
     first cell is the register offset that controls the first PIRQ link routing.
     The second cell is the total number of PIRQ links the router supports.
-- intel,pirq-mask : Specifies the IRQ mask reprenting the 16 IRQs in 8259 PIC.
-    Bit N is 1 means IRQ N is available to be routed.
+- intel,pirq-mask : Specifies the IRQ mask representing the 16 IRQs in the
+    8259 PIC. Bit N is 1 means IRQ N is available to be routed.
 - intel,pirq-routing : Specifies all PCI devices' IRQ routing information,
    encoded as 3 cells a group for a device. The first cell is the device's PCI
    bus number, device number and function number encoding with PCI_BDF() macro.