@@ -1612,11 +1612,27 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm)
aarch64_emit_move (dest, base);
return;
}
+
mem = force_const_mem (ptr_mode, imm);
gcc_assert (mem);
+
+ /* If we aren't generating PC relative literals, then
+ we need to expand the literal pool access carefully.
+ This is something that needs to be done in a number
+ of places, so could well live as a separate function. */
+ if (nopcrelative_literal_loads)
+ {
+ gcc_assert (can_create_pseudo_p ());
+ base = gen_reg_rtx (ptr_mode);
+ aarch64_expand_mov_immediate (base, XEXP (mem, 0));
+ mem = gen_rtx_MEM (ptr_mode, base);
+ }
+
if (mode != ptr_mode)
mem = gen_rtx_ZERO_EXTEND (mode, mem);
+
emit_insn (gen_rtx_SET (dest, mem));
+
return;
case SYMBOL_SMALL_TLSGD:
@@ -3728,9 +3744,10 @@ aarch64_classify_address (struct aarch64_address_info *info,
rtx sym, addend;
split_const (x, &sym, &addend);
- return (GET_CODE (sym) == LABEL_REF
- || (GET_CODE (sym) == SYMBOL_REF
- && CONSTANT_POOL_ADDRESS_P (sym)));
+ return ((GET_CODE (sym) == LABEL_REF
+ || (GET_CODE (sym) == SYMBOL_REF
+ && CONSTANT_POOL_ADDRESS_P (sym)
+ && !nopcrelative_literal_loads)));
}
return false;
@@ -4918,12 +4935,69 @@ aarch64_legitimize_reload_address (rtx *x_p,
}
+/* Return the reload icode required for a constant pool in mode. */
+static enum insn_code
+aarch64_constant_pool_reload_icode (machine_mode mode)
+{
+ switch (mode)
+ {
+ case SFmode:
+ return CODE_FOR_aarch64_reload_movcpsfdi;
+
+ case DFmode:
+ return CODE_FOR_aarch64_reload_movcpdfdi;
+
+ case TFmode:
+ return CODE_FOR_aarch64_reload_movcptfdi;
+
+ case V8QImode:
+ return CODE_FOR_aarch64_reload_movcpv8qidi;
+
+ case V16QImode:
+ return CODE_FOR_aarch64_reload_movcpv16qidi;
+
+ case V4HImode:
+ return CODE_FOR_aarch64_reload_movcpv4hidi;
+
+ case V8HImode:
+ return CODE_FOR_aarch64_reload_movcpv8hidi;
+
+ case V2SImode:
+ return CODE_FOR_aarch64_reload_movcpv2sidi;
+
+ case V4SImode:
+ return CODE_FOR_aarch64_reload_movcpv4sidi;
+
+ case V2DImode:
+ return CODE_FOR_aarch64_reload_movcpv2didi;
+
+ case V2DFmode:
+ return CODE_FOR_aarch64_reload_movcpv2dfdi;
+
+ default:
+ gcc_unreachable ();
+ }
+
+ gcc_unreachable ();
+}
static reg_class_t
aarch64_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x,
reg_class_t rclass,
machine_mode mode,
secondary_reload_info *sri)
{
+
+ /* If we have to disable direct literal pool loads and stores because the
+ function is too big, then we need a scratch register. */
+ if (MEM_P (x) && GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x)
+ && (SCALAR_FLOAT_MODE_P (GET_MODE (x))
+ || targetm.vector_mode_supported_p (GET_MODE (x)))
+ && nopcrelative_literal_loads)
+ {
+ sri->icode = aarch64_constant_pool_reload_icode (mode);
+ return NO_REGS;
+ }
+
/* Without the TARGET_SIMD instructions we cannot move a Q register
to a Q register directly. We need a scratch. */
if (REG_P (x) && (mode == TFmode || mode == TImode) && mode == GET_MODE (x)
@@ -7543,6 +7617,17 @@ aarch64_override_options (void)
#endif
}
+ if (nopcrelative_literal_loads == 2)
+ nopcrelative_literal_loads = 0;
+
+ /* In the tiny memory model it makes no sense
+ to disallow non PC relative literal pool loads
+ as many other things will break anyway. */
+ if (nopcrelative_literal_loads
+ && (aarch64_cmodel == AARCH64_CMODEL_TINY
+ || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC))
+ nopcrelative_literal_loads = 0;
+
aarch64_register_fma_steering ();
aarch64_override_options_after_change ();
@@ -7697,7 +7782,16 @@ aarch64_classify_symbol (rtx x, rtx offset,
if (GET_CODE (x) == SYMBOL_REF)
{
if (aarch64_cmodel == AARCH64_CMODEL_LARGE)
- return SYMBOL_FORCE_TO_MEM;
+ {
+ /* This is alright even in PIC code as the constant
+ pool reference is always PC relative and within
+ the same translation unit. */
+ if (nopcrelative_literal_loads
+ && CONSTANT_POOL_ADDRESS_P (x))
+ return SYMBOL_SMALL_ABSOLUTE;
+ else
+ return SYMBOL_FORCE_TO_MEM;
+ }
if (aarch64_tls_symbol_p (x))
return aarch64_classify_tls_symbol (x);
@@ -4231,6 +4231,32 @@
;; -------------------------------------------------------------------
;; Reload support
;; -------------------------------------------------------------------
+;; Reload Scalar Floating point modes from constant pool.
+;; The AArch64 port doesn't have __int128 constant move support.
+(define_expand "aarch64_reload_movcp<ALLTF:mode><P:mode>"
+ [(set (match_operand:ALLTF 0 "register_operand" "=w")
+ (mem:ALLTF (match_operand 1 "aarch64_constant_pool_symref" "S")))
+ (clobber (match_operand:P 2 "register_operand" "=&r"))]
+ "TARGET_FLOAT && nopcrelative_literal_loads"
+ {
+ aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
+ emit_move_insn (operands[0], gen_rtx_MEM (<ALLTF:MODE>mode, operands[2]));
+ DONE;
+ }
+)
+
+;; Reload Vector modes from constant pool.
+(define_expand "aarch64_reload_movcp<VALL:mode><P:mode>"
+ [(set (match_operand:VALL 0 "register_operand" "=w")
+ (mem:VALL (match_operand 1 "aarch64_constant_pool_symref" "S")))
+ (clobber (match_operand:P 2 "register_operand" "=&r"))]
+ "TARGET_FLOAT && nopcrelative_literal_loads"
+ {
+ aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
+ emit_move_insn (operands[0], gen_rtx_MEM (<VALL:MODE>mode, operands[2]));
+ DONE;
+ }
+)
(define_expand "aarch64_reload_mov<mode>"
[(set (match_operand:TX 0 "register_operand" "=w")
@@ -124,3 +124,7 @@ Enum(aarch64_abi) String(ilp32) Value(AARCH64_ABI_ILP32)
EnumValue
Enum(aarch64_abi) String(lp64) Value(AARCH64_ABI_LP64)
+
+mnopc-relative-literal-loads
+Target Report Save Var(nopcrelative_literal_loads) Init(1)
+No PC relative literal loads.
@@ -362,3 +362,7 @@
(define_predicate "aarch64_simd_shift_imm_bitsize_di"
(and (match_code "const_int")
(match_test "IN_RANGE (INTVAL (op), 0, 64)")))
+
+(define_predicate "aarch64_constant_pool_symref"
+ (and (match_code "symbol_ref")
+ (match_test "CONSTANT_POOL_ADDRESS_P (op)")))
@@ -12496,6 +12496,14 @@ for @var{string} in this option are not guaranteed to be consistent
across releases.
This option is only intended to be useful when developing GCC.
+
+@item -mnopc-relative-literal-loads
+@opindex mnopcrelativeliteralloads
+Disable PC relative literal loads. If this option is used, literal
+pools are assumed to have a range of up to 4GiB and an appropriate
+instruction sequence is used. This option has no impact when used
+with @option{-mcmodel=tiny}.
+
@end table
@subsubsection @option{-march} and @option{-mcpu} Feature Modifiers