@@ -978,8 +978,8 @@
})
(define_expand "mov<mode>"
- [(set (match_operand:GPF 0 "nonimmediate_operand" "")
- (match_operand:GPF 1 "general_operand" ""))]
+ [(set (match_operand:ALLTF 0 "nonimmediate_operand" "")
+ (match_operand:ALLTF 1 "general_operand" ""))]
""
{
if (!TARGET_FLOAT)
@@ -1033,24 +1033,6 @@
f_loadd,f_stored,load1,store1,mov_reg")]
)
-(define_expand "movtf"
- [(set (match_operand:TF 0 "nonimmediate_operand" "")
- (match_operand:TF 1 "general_operand" ""))]
- ""
- {
- if (!TARGET_FLOAT)
- {
- aarch64_err_no_fpadvsimd (TFmode, "code");
- FAIL;
- }
-
- if (GET_CODE (operands[0]) == MEM
- && ! (GET_CODE (operands[1]) == CONST_DOUBLE
- && aarch64_float_const_zero_rtx_p (operands[1])))
- operands[1] = force_reg (TFmode, operands[1]);
- }
-)
-
(define_insn "*movtf_aarch64"
[(set (match_operand:TF 0
"nonimmediate_operand" "=w,?&r,w ,?r,w,?w,w,m,?r ,Ump,Ump")
@@ -38,6 +38,9 @@
;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes)
(define_mode_iterator GPF [SF DF])
+;; Iterator for all scalar floating point modes (SF, DF and TF)
+(define_mode_iterator ALLTF [SF DF TF])
+
;; Integer vector modes.
(define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])