| Message ID | 1437605072-22499-1-git-send-email-swarren@wwwdotorg.org |
|---|---|
| State | Accepted |
| Delegated to: | Tom Warren |
| Headers | show |
On 22 July 2015 at 16:44, Stephen Warren <swarren@wwwdotorg.org> wrote: > From: Thierry Reding <treding@nvidia.com> > > The encoding of the sub instruction used to handle CONFIG_SYS_MALLOC_F_LEN > can only accept certain values, and the set of acceptable values differs > between the AArch32 and AArch64 instructions sets. The default value of > CONFIG_SYS_MALLOC_F_LEN works with either ISA. Tegra uses a non-default > value that can only be encoded in the AArch32 ISA. Fix the AArch64 crt0 > assembly so it can handle completely arbitrary values. > > Signed-off-by: Thierry Reding <treding@nvidia.com> > [twarren: trimmed Thierry's patch to remove changes already present] > Signed-off-by: Tom Warren <twarren@nvidia.com> > [swarren, cleaned up patch, wrote description, re-wrote subject] > Signed-off-by: Stephen Warren <swarren@nvidia.com> > --- > arch/arm/lib/crt0_64.S | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) Reviewed-by: Simon Glass <sjg@chromium.org>
diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index bc9c53c308de..98a906ee111c 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -74,7 +74,8 @@ zero_gd: cmp x0, x18 b.gt zero_gd #if defined(CONFIG_SYS_MALLOC_F_LEN) - sub x0, x18, #CONFIG_SYS_MALLOC_F_LEN + ldr x0, =CONFIG_SYS_MALLOC_F_LEN + sub x0, x18, x0 str x0, [x18, #GD_MALLOC_BASE] #endif bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */