Message ID | 1437603903-2304-2-git-send-email-aalonso@freescale.com |
---|---|
State | Superseded |
Delegated to: | Stefano Babic |
Headers | show |
Hi Adrian, On 23/07/2015 00:24, Adrian Alonso wrote: > DCIMVAC is upgraded to DCCIMVAC for the individual processor > (Cortex-A7) that the DCIMVAC is executed on. > > We should follow the linux dma follow. Before DMA read, first > invalidate dcache then after DMA read, invalidate dcache again. > > With the DMA direction DMA_FROM_DEVICE, the dcache need be > invalidated again after the DMA completion. The reason is > that we need explicity make sure the dcache been invalidated > thus to get the DMA'ed memory correctly from the physical memory. > Any cache-line fill during the DMA operations such as the > pre-fetching can cause the DMA coherency issue, thus CPU get the stale data. > Pen has already sent this patch: https://patchwork.ozlabs.org/patch/488273/ Please do not copy and resend patches that are already enqueded. Instead, advise that your patches depend on some previous ones. Thanks. Best regards, Stefano Babic
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index c4719e6..0510bf0 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -341,6 +341,9 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) err = esdhc_setup_data(mmc, data); if(err) return err; + + if (data->flags & MMC_DATA_READ) + check_and_invalidate_dcache_range(cmd, data); } /* Figure out the transfer arguments */ @@ -437,6 +440,11 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) } } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); + /* + * Need invalidate the dcache here again to avoid any + * cache-fill during the DMA operations such as the + * speculative pre-fetching etc. + */ if (data->flags & MMC_DATA_READ) check_and_invalidate_dcache_range(cmd, data); #endif