From patchwork Wed Apr 7 17:51:24 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 49628 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 4AAA4B7D24 for ; Thu, 8 Apr 2010 04:30:04 +1000 (EST) Received: from localhost ([127.0.0.1]:54362 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NzZsk-0007hF-Pw for incoming@patchwork.ozlabs.org; Wed, 07 Apr 2010 14:21:42 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NzZQJ-0006Cl-2j for qemu-devel@nongnu.org; Wed, 07 Apr 2010 13:52:19 -0400 Received: from [140.186.70.92] (port=55426 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NzZQ8-000671-DQ for qemu-devel@nongnu.org; Wed, 07 Apr 2010 13:52:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1NzZPm-0007LK-Ad for qemu-devel@nongnu.org; Wed, 07 Apr 2010 13:52:08 -0400 Received: from hall.aurel32.net ([88.191.82.174]:45327) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1NzZPj-0007KL-Df for qemu-devel@nongnu.org; Wed, 07 Apr 2010 13:51:44 -0400 Received: from [2a01:e35:2e80:2fb0:21e:8cff:feb0:693b] (helo=volta.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1NzZPi-00011c-D1; Wed, 07 Apr 2010 19:51:42 +0200 Received: from aurel32 by volta.aurel32.net with local (Exim 4.71) (envelope-from ) id 1NzZPd-0001yM-Bp; Wed, 07 Apr 2010 19:51:37 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Wed, 7 Apr 2010 19:51:24 +0200 Message-Id: <1270662685-7379-18-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1270662685-7379-1-git-send-email-aurelien@aurel32.net> References: <1270662685-7379-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: Andrzej Zaborowski , Aurelien Jarno Subject: [Qemu-devel] [PATCH 17/18] tcg/arm: optimize register allocation order X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The beginning of the register allocation order list on the TCG arm target matches the list of clobbered registers. This means that when an helper is called, there is almost always clobbered registers that have to be spilled. Signed-off-by: Aurelien Jarno --- tcg/arm/tcg-target.c | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index 91542bd..03fe11c 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -65,10 +65,6 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { #endif static const int tcg_target_reg_alloc_order[] = { - TCG_REG_R0, - TCG_REG_R1, - TCG_REG_R2, - TCG_REG_R3, TCG_REG_R4, TCG_REG_R5, TCG_REG_R6, @@ -77,8 +73,12 @@ static const int tcg_target_reg_alloc_order[] = { TCG_REG_R9, TCG_REG_R10, TCG_REG_R11, - TCG_REG_R12, TCG_REG_R13, + TCG_REG_R0, + TCG_REG_R1, + TCG_REG_R2, + TCG_REG_R3, + TCG_REG_R12, TCG_REG_R14, };