[U-Boot,v2,08/15] cgtqmx6eval: Add SPI NOR flash support

Add SPI NOR support:

=> sf probe
SF: Detected SST25VF032B with page size 256 Bytes, erase size 4 KiB, total 4 MiB

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
---

Changes in v2: None

 board/congatec/cgtqmx6eval/cgtqmx6eval.c | 23 +++++++++++++++++++++++
 include/configs/cgtqmx6eval.h            | 10 ++++++++++
 2 files changed, 33 insertions(+)

On 14 July 2015 at 00:31, Otavio Salvador <otavio@ossystems.com.br> wrote:
> Add SPI NOR support:
>
> => sf probe
> SF: Detected SST25VF032B with page size 256 Bytes, erase size 4 KiB, total 4 MiB
>
> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
> ---

Reviewed-by: Jagan Teki <jteki@openedev.com>

>
> Changes in v2: None
>
>  board/congatec/cgtqmx6eval/cgtqmx6eval.c | 23 +++++++++++++++++++++++
>  include/configs/cgtqmx6eval.h            | 10 ++++++++++
>  2 files changed, 33 insertions(+)
>
> diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
> index 1ae126c..197bb89 100644
> --- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c
> +++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
> @@ -27,6 +27,10 @@ DECLARE_GLOBAL_DATA_PTR;
>  #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |\
>         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
>
> +#define SPI_PAD_CTRL (PAD_CTL_HYS |                            \
> +       PAD_CTL_SPEED_MED |             \
> +       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
> +
>  int dram_init(void)
>  {
>         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
> @@ -77,11 +81,24 @@ static iomux_v3_cfg_t const usdhc4_pads[] = {
>         MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
>  };
>
> +static iomux_v3_cfg_t const ecspi1_pads[] = {
> +       MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
> +       MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
> +       MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
> +       MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
>  static void setup_iomux_uart(void)
>  {
>         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
>  }
>
> +void setup_spinor(void)
> +{
> +       imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
> +       gpio_direction_output(IMX_GPIO_NR(3, 19), 0);
> +}
> +
>  #ifdef CONFIG_FSL_ESDHC
>  static struct fsl_esdhc_cfg usdhc_cfg[] = {
>         {USDHC2_BASE_ADDR},
> @@ -158,6 +175,7 @@ int board_mmc_init(bd_t *bis)
>  int board_early_init_f(void)
>  {
>         setup_iomux_uart();
> +       setup_spinor();
>
>         return 0;
>  }
> @@ -177,6 +195,11 @@ int checkboard(void)
>         return 0;
>  }
>
> +int board_spi_cs_gpio(unsigned bus, unsigned cs)
> +{
> +       return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -EINVAL;
> +}
> +
>  #ifdef CONFIG_CMD_BMODE
>  static const struct boot_mode board_boot_modes[] = {
>         /* 4 bit bus width */
> diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h
> index 9d9e388..b0ceffc 100644
> --- a/include/configs/cgtqmx6eval.h
> +++ b/include/configs/cgtqmx6eval.h
> @@ -29,6 +29,16 @@
>  /* MMC Configs */
>  #define CONFIG_SYS_FSL_ESDHC_ADDR      0
>
> +/* SPI NOR */
> +#define CONFIG_CMD_SF
> +#define CONFIG_SPI_FLASH
> +#define CONFIG_SPI_FLASH_STMICRO
> +#define CONFIG_SPI_FLASH_SST
> +#define CONFIG_MXC_SPI
> +#define CONFIG_SF_DEFAULT_BUS          0
> +#define CONFIG_SF_DEFAULT_SPEED                20000000
> +#define CONFIG_SF_DEFAULT_MODE         (SPI_MODE_0)
> +
>  /* Miscellaneous commands */
>  #define CONFIG_CMD_BMODE
>
> --
> 2.4.5
>
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On Thu, Aug 13, 2015 at 4:07 PM, Jagan Teki <jteki@openedev.com> wrote:
> On 14 July 2015 at 00:31, Otavio Salvador <otavio@ossystems.com.br> wrote:
>> Add SPI NOR support:
>>
>> => sf probe
>> SF: Detected SST25VF032B with page size 256 Bytes, erase size 4 KiB, total 4 MiB
>>
>> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
>> ---
>
> Reviewed-by: Jagan Teki <jteki@openedev.com>

We will send it again as part of SPL support as we want to protect the
manufactor area to avoid any bad surprise for end users.