@@ -113,6 +113,25 @@ int board_mmc_getcd(struct mmc *mmc)
return ret;
}
+int board_mmc_getwp(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC2_BASE_ADDR:
+ return -1; /* no write protection for onboard \B5SD */
+ case USDHC3_BASE_ADDR:
+ return -1; /* no write protection for eMMC */
+ case USDHC4_BASE_ADDR:
+ gpio_direction_input(IMX_GPIO_NR(2, 7));
+ ret = gpio_get_value(IMX_GPIO_NR(2, 7));
+ break;
+ }
+
+ return ret;
+}
+
int board_mmc_init(bd_t *bis)
{
s32 status = 0;
Add board_mmc_getwp() for reading the ESDHC write-protect pin. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> --- Changes in v2: None board/congatec/cgtqmx6eval/cgtqmx6eval.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)