| Message ID | 1436585927-18677-1-git-send-email-Peng.Fan@freescale.com |
|---|---|
| State | Awaiting Upstream |
| Headers | show |
On 11/07/2015 05:38, Peng Fan wrote: > Add cpu type for i.MX6QP/DP. > > This patch also fix is_mx6dqp(), since get_cpu_rev can return MXC_CPU_MX6QP > and MXC_CPU_MX6DP, we should use: > (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)). > > Signed-off-by: Peng Fan <Peng.Fan@freescale.com> > Acked-by: Stefano Babic <sbabic@denx.de> > --- > > Changes v5: > Refine commit msg > Add Stefano's Acked-by > > Changes v4: > Address Fabio's comments, Change Quad-Plus to Dual-Plus for i.MX6DP. > > Changes v3: > New patch > This patch is to make print_cpuinfo display correct cpu info,and fix is_mx6dqp > > Changes v2: > none > > arch/arm/cpu/armv7/mx6/soc.c | 11 +++++++++-- > arch/arm/imx-common/cpu.c | 4 ++++ > arch/arm/include/asm/arch-imx/cpu.h | 2 ++ > arch/arm/include/asm/arch-mx6/sys_proto.h | 4 +--- > 4 files changed, 16 insertions(+), 5 deletions(-) > > diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c > index 29de624..d3a3b2e 100644 > --- a/arch/arm/cpu/armv7/mx6/soc.c > +++ b/arch/arm/cpu/armv7/mx6/soc.c > @@ -62,12 +62,12 @@ u32 get_cpu_rev(void) > struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; > u32 reg = readl(&anatop->digprog_sololite); > u32 type = ((reg >> 16) & 0xff); > - u32 major; > + u32 major, cfg = 0; > > if (type != MXC_CPU_MX6SL) { > reg = readl(&anatop->digprog); > struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; > - u32 cfg = readl(&scu->config) & 3; > + cfg = readl(&scu->config) & 3; > type = ((reg >> 16) & 0xff); > if (type == MXC_CPU_MX6DL) { > if (!cfg) > @@ -81,6 +81,13 @@ u32 get_cpu_rev(void) > > } > major = ((reg >> 8) & 0xff); > + if ((major >= 1) && > + ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) { > + major--; > + type = MXC_CPU_MX6QP; > + if (cfg == 1) > + type = MXC_CPU_MX6DP; > + } > reg &= 0xff; /* mx6 silicon revision */ > return (type << 12) | (reg + (0x10 * (major + 1))); > } > diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c > index 5e56cfe..096d22e 100644 > --- a/arch/arm/imx-common/cpu.c > +++ b/arch/arm/imx-common/cpu.c > @@ -122,6 +122,10 @@ unsigned imx_ddr_size(void) > const char *get_imx_type(u32 imxtype) > { > switch (imxtype) { > + case MXC_CPU_MX6QP: > + return "6QP"; /* Quad-Plus version of the mx6 */ > + case MXC_CPU_MX6DP: > + return "6DP"; /* Dual-Plus version of the mx6 */ > case MXC_CPU_MX6Q: > return "6Q"; /* Quad-core version of the mx6 */ > case MXC_CPU_MX6D: > diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h > index 4715f4e..99e0e32 100644 > --- a/arch/arm/include/asm/arch-imx/cpu.h > +++ b/arch/arm/include/asm/arch-imx/cpu.h > @@ -12,6 +12,8 @@ > #define MXC_CPU_MX6Q 0x63 > #define MXC_CPU_MX6D 0x64 > #define MXC_CPU_MX6SOLO 0x65 /* dummy ID */ > +#define MXC_CPU_MX6DP 0x68 > +#define MXC_CPU_MX6QP 0x69 > > #define CS0_128 0 > #define CS0_64M_CS1_64M 1 > diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h > index 28c77a4..eee8ca8 100644 > --- a/arch/arm/include/asm/arch-mx6/sys_proto.h > +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h > @@ -30,9 +30,7 @@ const char *get_imx_type(u32 imxtype); > unsigned imx_ddr_size(void); > void set_chipselect_size(int const); > > -#define is_mx6dqp() ((is_cpu_type(MXC_CPU_MX6Q) || \ > - is_cpu_type(MXC_CPU_MX6D)) && \ > - (soc_rev() >= CHIP_REV_2_0)) > +#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) > > /* > * Initializes on-chip ethernet controllers. > Applied to u-boot-imx, thanks ! Best regards, Stefano Babic
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 29de624..d3a3b2e 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -62,12 +62,12 @@ u32 get_cpu_rev(void) struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; u32 reg = readl(&anatop->digprog_sololite); u32 type = ((reg >> 16) & 0xff); - u32 major; + u32 major, cfg = 0; if (type != MXC_CPU_MX6SL) { reg = readl(&anatop->digprog); struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; - u32 cfg = readl(&scu->config) & 3; + cfg = readl(&scu->config) & 3; type = ((reg >> 16) & 0xff); if (type == MXC_CPU_MX6DL) { if (!cfg) @@ -81,6 +81,13 @@ u32 get_cpu_rev(void) } major = ((reg >> 8) & 0xff); + if ((major >= 1) && + ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) { + major--; + type = MXC_CPU_MX6QP; + if (cfg == 1) + type = MXC_CPU_MX6DP; + } reg &= 0xff; /* mx6 silicon revision */ return (type << 12) | (reg + (0x10 * (major + 1))); } diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index 5e56cfe..096d22e 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -122,6 +122,10 @@ unsigned imx_ddr_size(void) const char *get_imx_type(u32 imxtype) { switch (imxtype) { + case MXC_CPU_MX6QP: + return "6QP"; /* Quad-Plus version of the mx6 */ + case MXC_CPU_MX6DP: + return "6DP"; /* Dual-Plus version of the mx6 */ case MXC_CPU_MX6Q: return "6Q"; /* Quad-core version of the mx6 */ case MXC_CPU_MX6D: diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 4715f4e..99e0e32 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -12,6 +12,8 @@ #define MXC_CPU_MX6Q 0x63 #define MXC_CPU_MX6D 0x64 #define MXC_CPU_MX6SOLO 0x65 /* dummy ID */ +#define MXC_CPU_MX6DP 0x68 +#define MXC_CPU_MX6QP 0x69 #define CS0_128 0 #define CS0_64M_CS1_64M 1 diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index 28c77a4..eee8ca8 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -30,9 +30,7 @@ const char *get_imx_type(u32 imxtype); unsigned imx_ddr_size(void); void set_chipselect_size(int const); -#define is_mx6dqp() ((is_cpu_type(MXC_CPU_MX6Q) || \ - is_cpu_type(MXC_CPU_MX6D)) && \ - (soc_rev() >= CHIP_REV_2_0)) +#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) /* * Initializes on-chip ethernet controllers.