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PR target/66813: gcc.target/i386/asm-flag-5.c failed with -march=pentium

Message ID CAFULd4brsiMRtTukn=qRmF1Y9e1uLMyhBHQwnE-apK=ZL-k17Q@mail.gmail.com
State New
Headers show

Commit Message

Uros Bizjak July 10, 2015, 10:08 a.m. UTC 
On Thu, Jul 9, 2015 at 3:15 PM, Uros Bizjak <ubizjak@gmail.com> wrote:

>> gen_rtx_ZERO_EXTEND isn't suitable in ix86_md_asm_adjust since ZERO_EXTEND
>> may be expaned.  We should call gen_zero_extendqiXi2 instead.
>>
>> OK for trunk?
>
> No, your patch will clobber flags when multiple flag outputs are used.
>
> (I plan to rewrite x86 zero_extend patterns to use preferred_for_size
> attribute with peepholes, this will magically solve this bug and
> readeflags-1.c failure).

No, the above mentioned patch won't fly, it limits AND insn operands
too much with "q" constraint.

So, the patch below is what I plan to commit after
bootstrap/regression test on x86_64-linux-gnu {,-m32}.

2015-07-10  Uros Bizjak  <ubizjak@gmail.com>

    PR target/66813
    * config/i386/i386.c (ix86_md_asm_adjust): Emit movstrictqi
    sequence for TARGET_ZERO_EXTEND_WITH_AND targets.

testsuite/ChangeLog:

2015-07-10  Uros Bizjak  <ubizjak@gmail.com>

    PR target/66813
    * gcc.target/i386/pr66813.c: New test.

Uros.
diff mbox

Patch

Index: testsuite/gcc.target/i386/pr66813.c
===================================================================
--- testsuite/gcc.target/i386/pr66813.c	(revision 0)
+++ testsuite/gcc.target/i386/pr66813.c	(revision 0)
@@ -0,0 +1,4 @@ 
+/* { dg-do compile { target { ia32 } } } */
+/* { dg-options "-march=pentium" } */
+
+#include "asm-flag-5.c"
Index: config/i386/i386.c
===================================================================
--- config/i386/i386.c	(revision 225648)
+++ config/i386/i386.c	(working copy)
@@ -45842,7 +45842,17 @@  ix86_md_asm_adjust (vec<rtx> &outputs, vec<rtx> &/
 	{
 	  rtx destqi = gen_reg_rtx (QImode);
 	  emit_insn (gen_rtx_SET (destqi, x));
-	  x = gen_rtx_ZERO_EXTEND (dest_mode, destqi);
+
+	  if (TARGET_ZERO_EXTEND_WITH_AND
+	      && optimize_function_for_speed_p (cfun))
+	    {
+	      x = force_reg (dest_mode, const0_rtx);
+
+	      emit_insn (gen_movstrictqi
+			 (gen_lowpart (QImode, x), destqi));
+	    }
+	  else
+	    x = gen_rtx_ZERO_EXTEND (dest_mode, destqi);
 	}
       emit_insn (gen_rtx_SET (dest, x));
     }