diff mbox

[v2] ich9: initialise RCBA register through LPC interface

Message ID 1436486641-11808-1-git-send-email-pcacjr@zytor.com
State New
Headers show

Commit Message

Paulo Alcantara July 10, 2015, 12:04 a.m. UTC
This patch initialises root complex register block BAR in order to
support TCO watchdog emulation features on QEMU.

Cc: Kevin O'Connor <kevin@koconnor.net>
Cc: Gerd Hofmann <kraxel@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Paulo Alcantara <pcacjr@zytor.com>
---
v1 -> v2:
  - reserve RCBA address via e820 map
---
 src/fw/dev-q35.h | 3 +++
 src/fw/pciinit.c | 5 +++++
 2 files changed, 8 insertions(+)

Comments

Gerd Hoffmann July 14, 2015, 1:55 p.m. UTC | #1
On Do, 2015-07-09 at 21:04 -0300, Paulo Alcantara wrote:
> This patch initialises root complex register block BAR in order to
> support TCO watchdog emulation features on QEMU.

qemu patches are merged, committed this one too now.
Also cherry-picked into 1.8-stable.

So, time to roll 1.8.3?  Anything else pending?

cheers,
  Gerd
Paulo Alcantara July 14, 2015, 8:45 p.m. UTC | #2
On Tue, 14 Jul 2015 15:55:24 +0200
Gerd Hoffmann <kraxel@redhat.com> wrote:

> On Do, 2015-07-09 at 21:04 -0300, Paulo Alcantara wrote:
> > This patch initialises root complex register block BAR in order to
> > support TCO watchdog emulation features on QEMU.
> 
> qemu patches are merged, committed this one too now.
> Also cherry-picked into 1.8-stable.

Alright. Thanks!

> So, time to roll 1.8.3?  Anything else pending?

Yep. No, that's all.

Paulo
diff mbox

Patch

diff --git a/src/fw/dev-q35.h b/src/fw/dev-q35.h
index c6f8bd9..201825d 100644
--- a/src/fw/dev-q35.h
+++ b/src/fw/dev-q35.h
@@ -27,6 +27,9 @@ 
 #define ICH9_LPC_GEN_PMCON_1_SMI_LOCK  (1 << 4)
 #define ICH9_LPC_PORT_ELCR1            0x4d0
 #define ICH9_LPC_PORT_ELCR2            0x4d1
+#define ICH9_LPC_RCBA                  0xf0
+#define ICH9_LPC_RCBA_ADDR             0xfed1c000
+#define ICH9_LPC_RCBA_EN               0x1
 #define PCI_DEVICE_ID_INTEL_ICH9_SMBUS 0x2930
 #define ICH9_SMB_SMB_BASE              0x20
 #define ICH9_SMB_HOSTC                 0x40
diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c
index 45870f2..3ad84ba 100644
--- a/src/fw/pciinit.c
+++ b/src/fw/pciinit.c
@@ -183,6 +183,11 @@  static void mch_isa_bridge_setup(struct pci_device *dev, void *arg)
     /* acpi enable, SCI: IRQ9 000b = irq9*/
     pci_config_writeb(bdf, ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_ACPI_EN);
 
+    /* set root complex register block BAR */
+    pci_config_writel(bdf, ICH9_LPC_RCBA,
+                      ICH9_LPC_RCBA_ADDR | ICH9_LPC_RCBA_EN);
+    add_e820(ICH9_LPC_RCBA_ADDR, 16*1024, E820_RESERVED);
+
     acpi_pm1a_cnt = acpi_pm_base + 0x04;
     pmtimer_setup(acpi_pm_base + 0x08);
 }