| Message ID | 1436163304-6167-5-git-send-email-serge.vakulenko@gmail.com |
|---|---|
| State | New |
| Headers | show |
On 2015-07-05 23:14, Serge Vakulenko wrote: > Needed for pic32mx (M4K) and pic32mz (microAptivUP) simulation. > > Signed-off-by: Serge Vakulenko <serge.vakulenko@gmail.com> > --- > target-mips/translate_init.c | 46 ++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 46 insertions(+) > > diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c > index ddfaff8..8786321 100644 > --- a/target-mips/translate_init.c > +++ b/target-mips/translate_init.c > @@ -190,6 +190,26 @@ static const mips_def_t mips_defs[] = > .mmu_type = MMU_TYPE_FMT, > }, > { > + /* Configuration for Microchip PIC32MX microcontroller. */ > + .name = "M4K", > + .CP0_PRid = 0x00018700, > + .CP0_Config0 = MIPS_CONFIG0 | (2 << CP0C0_K23) | (2 << CP0C0_KU) | > + (1 << CP0C0_BM) | (1 << CP0C0_AR) | > + (MMU_TYPE_FMT << CP0C0_MT), > + .CP0_Config1 = (1U << CP0C1_M) | (1 << CP0C1_CA) | (1 << CP0C1_EP), > + .CP0_Config2 = MIPS_CONFIG2, > + .CP0_Config3 = (1 << CP0C3_VEIC) | (1 << CP0C3_VInt), > + .CP0_LLAddr_rw_bitmask = 0, > + .CP0_LLAddr_shift = 4, > + .SYNCI_Step = 32, > + .CCRes = 2, > + .CP0_Status_rw_bitmask = 0x1258FF17, > + .SEGBITS = 32, > + .PABITS = 32, > + .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, > + .mmu_type = MMU_TYPE_FMT, > + }, > + { > .name = "4KEc", > .CP0_PRid = 0x00019000, > .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | > @@ -389,6 +409,32 @@ static const mips_def_t mips_defs[] = > .mmu_type = MMU_TYPE_R4000, > }, > { > + /* Configuration for Microchip PIC32MZ microcontroller. */ > + .name = "microAptivUP", > + .CP0_PRid = 0x00019e00, > + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | > + (MMU_TYPE_R4000 << CP0C0_MT), > + .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | (1 << CP0C1_PC), > + .CP0_Config2 = MIPS_CONFIG2, > + .CP0_Config3 = (1 << CP0C3_M) | (1 << CP0C3_IPLW) | (1 << CP0C3_MCU) | > + (2 << CP0C3_ISA) | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | > + (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) | (1 << CP0C3_VEIC) | > + (1 << CP0C3_VInt), > + .CP0_Config4 = (1 << CP0C4_M), > + .CP0_Config5 = (1 << CP0C5_NFExists), > + .CP0_Config6 = 0, > + .CP0_Config7 = 0, > + .CP0_LLAddr_rw_bitmask = 0, > + .CP0_LLAddr_shift = 4, > + .SYNCI_Step = 32, > + .CCRes = 2, > + .CP0_Status_rw_bitmask = 0x1278FF17, > + .SEGBITS = 32, > + .PABITS = 32, > + .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS | ASE_DSP | ASE_DSPR2, > + .mmu_type = MMU_TYPE_R4000, > + }, > + { > /* A generic CPU providing MIPS32 Release 5 features. > FIXME: Eventually this should be replaced by a real CPU model. */ > .name = "mips32r5-generic", Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Hi Serge, On 06/07/15 07:14, Serge Vakulenko wrote: > Needed for pic32mx (M4K) and pic32mz (microAptivUP) simulation. > > Signed-off-by: Serge Vakulenko <serge.vakulenko@gmail.com> > --- > target-mips/translate_init.c | 46 ++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 46 insertions(+) This patch looks good, but these new cores have VEIC support enabled so I think it should go together with patch #3 which actually implements EIC. These patches don't need to wait until entire series is ready, thus if you address Aurelien's comment related to introducing CP0Ca_RIPL_mask in patch #3, then I could cherry-pick these two patches and apply to target-mips queue. Thanks, Leon
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index ddfaff8..8786321 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -190,6 +190,26 @@ static const mips_def_t mips_defs[] = .mmu_type = MMU_TYPE_FMT, }, { + /* Configuration for Microchip PIC32MX microcontroller. */ + .name = "M4K", + .CP0_PRid = 0x00018700, + .CP0_Config0 = MIPS_CONFIG0 | (2 << CP0C0_K23) | (2 << CP0C0_KU) | + (1 << CP0C0_BM) | (1 << CP0C0_AR) | + (MMU_TYPE_FMT << CP0C0_MT), + .CP0_Config1 = (1U << CP0C1_M) | (1 << CP0C1_CA) | (1 << CP0C1_EP), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = (1 << CP0C3_VEIC) | (1 << CP0C3_VInt), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x1258FF17, + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, + .mmu_type = MMU_TYPE_FMT, + }, + { .name = "4KEc", .CP0_PRid = 0x00019000, .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | @@ -389,6 +409,32 @@ static const mips_def_t mips_defs[] = .mmu_type = MMU_TYPE_R4000, }, { + /* Configuration for Microchip PIC32MZ microcontroller. */ + .name = "microAptivUP", + .CP0_PRid = 0x00019e00, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | (1 << CP0C1_PC), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = (1 << CP0C3_M) | (1 << CP0C3_IPLW) | (1 << CP0C3_MCU) | + (2 << CP0C3_ISA) | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | + (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) | (1 << CP0C3_VEIC) | + (1 << CP0C3_VInt), + .CP0_Config4 = (1 << CP0C4_M), + .CP0_Config5 = (1 << CP0C5_NFExists), + .CP0_Config6 = 0, + .CP0_Config7 = 0, + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x1278FF17, + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS | ASE_DSP | ASE_DSPR2, + .mmu_type = MMU_TYPE_R4000, + }, + { /* A generic CPU providing MIPS32 Release 5 features. FIXME: Eventually this should be replaced by a real CPU model. */ .name = "mips32r5-generic",
Needed for pic32mx (M4K) and pic32mz (microAptivUP) simulation. Signed-off-by: Serge Vakulenko <serge.vakulenko@gmail.com> --- target-mips/translate_init.c | 46 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+)