From patchwork Sat Jul 4 16:39:58 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 491287 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id E6698140787 for ; Sun, 5 Jul 2015 18:30:31 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753849AbbGEIaQ (ORCPT ); Sun, 5 Jul 2015 04:30:16 -0400 Received: from condef001-v.nifty.com ([210.131.4.238]:52656 "EHLO condef001-v.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752657AbbGEIaL (ORCPT ); Sun, 5 Jul 2015 04:30:11 -0400 X-Greylist: delayed 345 seconds by postgrey-1.27 at vger.kernel.org; Sun, 05 Jul 2015 04:30:11 EDT Received: from conuserg009-v.nifty.com ([10.16.229.196])by condef001-v.nifty.com with ESMTP id t64Gf1Sn024481; Sun, 5 Jul 2015 01:41:01 +0900 Received: from grover.sesame (FL1-125-192-212-42.osk.mesh.ad.jp [125.192.212.42]) (authenticated) by conuserg009-v.nifty.com with ESMTP id t64Ge5Ra024567; Sun, 5 Jul 2015 01:40:09 +0900 X-Nifty-SrcIP: [125.192.212.42] From: Masahiro Yamada To: linux-gpio@vger.kernel.org Cc: Masahiro Yamada , Linus Walleij , linux-kernel@vger.kernel.org, Alexandre Courbot , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2] gpio: UniPhier: add driver for UniPhier GPIO controller Date: Sun, 5 Jul 2015 01:39:58 +0900 Message-Id: <1436027998-820-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This GPIO controller device is used on UniPhier SoCs. Signed-off-by: Masahiro Yamada --- Changes in v2: - Fix typos in the comment block drivers/gpio/Kconfig | 6 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-uniphier.c | 273 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 280 insertions(+) create mode 100644 drivers/gpio/gpio-uniphier.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 4c9fa58..37cb4f2 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -462,6 +462,12 @@ config GPIO_TZ1090_PDC help Say yes here to support Toumaz Xenif TZ1090 PDC GPIOs. +config GPIO_UNIPHIER + tristate "UniPhier GPIO" + depends on ARCH_UNIPHIER && OF_GPIO + help + Say yes here to support UniPhier GPIOs. + config GPIO_VF610 def_bool y depends on ARCH_MXC && SOC_VF610 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index f82cd67..3538b0c 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -102,6 +102,7 @@ obj-$(CONFIG_GPIO_TWL6040) += gpio-twl6040.o obj-$(CONFIG_GPIO_TZ1090) += gpio-tz1090.o obj-$(CONFIG_GPIO_TZ1090_PDC) += gpio-tz1090-pdc.o obj-$(CONFIG_GPIO_UCB1400) += gpio-ucb1400.o +obj-$(CONFIG_GPIO_UNIPHIER) += gpio-uniphier.o obj-$(CONFIG_GPIO_VF610) += gpio-vf610.o obj-$(CONFIG_GPIO_VIPERBOARD) += gpio-viperboard.o obj-$(CONFIG_GPIO_VR41XX) += gpio-vr41xx.o diff --git a/drivers/gpio/gpio-uniphier.c b/drivers/gpio/gpio-uniphier.c new file mode 100644 index 0000000..96400d6 --- /dev/null +++ b/drivers/gpio/gpio-uniphier.c @@ -0,0 +1,273 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +/* + * Unfortunately, the hardware specification adopts weird GPIO pin labeling. + * The ports are named as + * PORT00, PORT01, PORT02, ..., PORT07, + * PORT10, PORT11, PORT12, ..., PORT17, + * PORT20, PORT21, PORT22, ..., PORT27, + * ... + * PORT90, PORT91, PORT92, ..., PORT97, + * PORT100, PORT101, PORT102, ..., PORT107, + * ... + * + * The PORTs with 8 or 9 in the one's place are missing, i.e. the one's place + * is octal, while the other places are decimal. If we handle the port numbers + * as seen in the hardware documents, the GPIO offsets must be non-contiguous. + * It is possible to have sparse GPIO pins, but not handy for GPIO range + * mappings, register accessing, etc. + * + * To make things simpler (for driver and device tree implementation), this + * driver takes contiguously-numbered GPIO offsets. GPIO consumers should make + * sure to convert the PORT number into the one that fits in this driver. + * The conversion logic is very easy math, for example, + * PORT15 --> GPIO offset 13 (8 * 1 + 5) + * PORT123 --> GPIO offset 99 (8 * 12 + 3) + */ +#define UNIPHIER_GPIO_PORTS_PER_BANK 8 +#define UNIPHIER_GPIO_BANK_MASK \ + ((1UL << (UNIPHIER_GPIO_PORTS_PER_BANK)) - 1) + +#define UNIPHIER_GPIO_REG_DATA 0 /* data */ +#define UNIPHIER_GPIO_REG_DIR 4 /* direction (1:in, 0:out) */ + +struct uniphier_gpio_priv { + struct of_mm_gpio_chip mmchip; + spinlock_t lock; +}; + +static unsigned uniphier_gpio_bank_to_reg(unsigned bank, unsigned reg_type) +{ + unsigned reg; + + reg = (bank + 1) * 8 + reg_type; + + /* + * Unfortunately, there is a register hole at offset 0x90-0x9f. + * Add 0x10 when crossing the hole. + */ + if (reg >= 0x90) + reg += 0x10; + + return reg; +} + +static void uniphier_gpio_bank_write(struct gpio_chip *chip, + unsigned bank, unsigned reg_type, + unsigned mask, unsigned value) +{ + struct of_mm_gpio_chip *mmchip = to_of_mm_gpio_chip(chip); + struct uniphier_gpio_priv *priv; + unsigned long flags; + unsigned reg; + u32 tmp; + + if (!mask) + return; + + priv = container_of(mmchip, struct uniphier_gpio_priv, mmchip); + + reg = uniphier_gpio_bank_to_reg(bank, reg_type); + + /* + * Note + * regmap_update_bits() should not be used here. + * + * The DATA registers return the current readback of pins, not the + * previously written data when they are configured as "input". + * The DATA registers must be overwritten even if the data you are + * going to write is the same as what readl() has returned. + * + * regmap_update_bits() does not write back if the data is not changed. + */ + spin_lock_irqsave(&priv->lock, flags); + tmp = readl(mmchip->regs + reg); + tmp &= ~mask; + tmp |= mask & value; + writel(tmp, mmchip->regs + reg); + spin_unlock_irqrestore(&priv->lock, flags); +} + +static void uniphier_gpio_offset_write(struct gpio_chip *chip, unsigned offset, + unsigned reg_type, int value) +{ + unsigned bank = offset / UNIPHIER_GPIO_PORTS_PER_BANK; + unsigned bit = offset % UNIPHIER_GPIO_PORTS_PER_BANK; + + uniphier_gpio_bank_write(chip, bank, reg_type, BIT(bit), value << bit); +} + +static int uniphier_gpio_offset_read(struct gpio_chip *chip, unsigned offset, + unsigned reg_type) +{ + struct of_mm_gpio_chip *mmchip = to_of_mm_gpio_chip(chip); + unsigned bank = offset / UNIPHIER_GPIO_PORTS_PER_BANK; + unsigned bit = offset % UNIPHIER_GPIO_PORTS_PER_BANK; + unsigned reg; + + reg = uniphier_gpio_bank_to_reg(bank, reg_type); + + return readl(mmchip->regs + reg) & BIT(bit) ? 1 : 0; +} + +static int uniphier_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + return pinctrl_request_gpio(chip->base + offset); +} + +static void uniphier_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + pinctrl_free_gpio(chip->base + offset); +} + +static int uniphier_gpio_get_direction(struct gpio_chip *chip, unsigned offset) +{ + return uniphier_gpio_offset_read(chip, UNIPHIER_GPIO_REG_DIR, offset) ? + GPIOF_DIR_IN : GPIOF_DIR_OUT; +} + +static int uniphier_gpio_direction_input(struct gpio_chip *chip, + unsigned offset) +{ + uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_REG_DIR, 1); + + return 0; +} + +static int uniphier_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_REG_DATA, value); + uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_REG_DIR, 0); + + return 0; +} + +static int uniphier_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + return uniphier_gpio_offset_read(chip, offset, UNIPHIER_GPIO_REG_DATA); +} + +static void uniphier_gpio_set(struct gpio_chip *chip, + unsigned offset, int value) +{ + uniphier_gpio_offset_write(chip, offset, UNIPHIER_GPIO_REG_DATA, value); +} + +static void uniphier_gpio_set_multiple(struct gpio_chip *chip, + unsigned long *mask, + unsigned long *bits) +{ + unsigned bank, shift, bank_mask, bank_bits; + int i; + + for (i = 0; i < chip->ngpio; i += UNIPHIER_GPIO_PORTS_PER_BANK) { + bank = i / UNIPHIER_GPIO_PORTS_PER_BANK; + shift = i % BITS_PER_LONG; + bank_mask = (mask[BIT_WORD(i)] >> shift) & + UNIPHIER_GPIO_BANK_MASK; + bank_bits = bits[BIT_WORD(i)] >> shift; + + uniphier_gpio_bank_write(chip, bank, UNIPHIER_GPIO_REG_DATA, + bank_mask, bank_bits); + } +} + +static int uniphier_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct uniphier_gpio_priv *priv; + u32 ngpio; + int ret; + + ret = of_property_read_u32(dev->of_node, "ngpio", &ngpio); + if (ret) { + dev_err(dev, "failed to get ngpio property\n"); + return ret; + } + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + spin_lock_init(&priv->lock); + + priv->mmchip.gc.dev = dev; + priv->mmchip.gc.owner = THIS_MODULE; + priv->mmchip.gc.request = uniphier_gpio_request; + priv->mmchip.gc.free = uniphier_gpio_free; + priv->mmchip.gc.get_direction = uniphier_gpio_get_direction; + priv->mmchip.gc.direction_input = uniphier_gpio_direction_input; + priv->mmchip.gc.direction_output = uniphier_gpio_direction_output; + priv->mmchip.gc.get = uniphier_gpio_get; + priv->mmchip.gc.set = uniphier_gpio_set; + priv->mmchip.gc.set_multiple = uniphier_gpio_set_multiple; + priv->mmchip.gc.ngpio = ngpio; + + ret = of_mm_gpiochip_add(dev->of_node, &priv->mmchip); + if (ret) { + dev_err(dev, "failed to add memory mapped gpiochip\n"); + return ret; + } + + platform_set_drvdata(pdev, priv); + + return 0; +} + +static int uniphier_gpio_remove(struct platform_device *pdev) +{ + struct uniphier_gpio_priv *priv = platform_get_drvdata(pdev); + + of_mm_gpiochip_remove(&priv->mmchip); + + return 0; +} + +static const struct of_device_id uniphier_gpio_match[] = { + { .compatible = "socionext,uniphier-gpio" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, uniphier_gpio_match); + +static struct platform_driver uniphier_gpio_driver = { + .probe = uniphier_gpio_probe, + .remove = uniphier_gpio_remove, + .driver = { + .name = "uniphier-gpio", + .of_match_table = uniphier_gpio_match, + }, +}; + +static int __init uniphier_gpio_init(void) +{ + return platform_driver_register(&uniphier_gpio_driver); +} +subsys_initcall(uniphier_gpio_init); + +static void __exit uniphier_gpio_exit(void) +{ + platform_driver_unregister(&uniphier_gpio_driver); +} +module_exit(uniphier_gpio_exit); + +MODULE_AUTHOR("Masahiro Yamada "); +MODULE_DESCRIPTION("UniPhier GPIO driver"); +MODULE_LICENSE("GPL");