diff mbox

[U-Boot,03/11] imx: mx6ul: Update imx registers head file

Message ID 1435834988-13032-4-git-send-email-Peng.Fan@freescale.com
State Changes Requested
Delegated to: Stefano Babic
Headers show

Commit Message

Peng Fan July 2, 2015, 11:03 a.m. UTC 
Update imx register base address for i.MX6UL

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
---
 arch/arm/include/asm/arch-mx6/imx-regs.h | 60 ++++++++++++++++++++++----------
 1 file changed, 41 insertions(+), 19 deletions(-)

Comments

Marek Vasut July 2, 2015, 6:30 p.m. UTC | #1 
On Thursday, July 02, 2015 at 01:03:00 PM, Peng Fan wrote:
> Update imx register base address for i.MX6UL
> 
> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
> Signed-off-by: Ye.Li <B37916@freescale.com>
> ---
>  arch/arm/include/asm/arch-mx6/imx-regs.h | 60
> ++++++++++++++++++++++---------- 1 file changed, 41 insertions(+), 19
> deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h
> b/arch/arm/include/asm/arch-mx6/imx-regs.h index 35a324c..d78daac 100644
> --- a/arch/arm/include/asm/arch-mx6/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
> @@ -9,7 +9,11 @@
> 
>  #define ARCH_MXC
> 
> +#ifdef CONFIG_MX6UL
> +#define CONFIG_SYS_CACHELINE_SIZE	64
> +#else

This doesn't seem like register base at all . This is cacheline size.
The patch description is thus misleading. It also fails to explain
this change ... probably because UL is C-A7 ?

>  #define CONFIG_SYS_CACHELINE_SIZE	32
> +#endif
[...]

Best regards,
Marek Vasut
Peng Fan July 2, 2015, 11:55 p.m. UTC | #2 
Hi Marek,

On Thu, Jul 02, 2015 at 08:30:30PM +0200, Marek Vasut wrote:
>On Thursday, July 02, 2015 at 01:03:00 PM, Peng Fan wrote:
>> Update imx register base address for i.MX6UL
>> 
>> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
>> Signed-off-by: Ye.Li <B37916@freescale.com>
>> ---
>>  arch/arm/include/asm/arch-mx6/imx-regs.h | 60
>> ++++++++++++++++++++++---------- 1 file changed, 41 insertions(+), 19
>> deletions(-)
>> 
>> diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h
>> b/arch/arm/include/asm/arch-mx6/imx-regs.h index 35a324c..d78daac 100644
>> --- a/arch/arm/include/asm/arch-mx6/imx-regs.h
>> +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
>> @@ -9,7 +9,11 @@
>> 
>>  #define ARCH_MXC
>> 
>> +#ifdef CONFIG_MX6UL
>> +#define CONFIG_SYS_CACHELINE_SIZE	64
>> +#else
>
>This doesn't seem like register base at all . This is cacheline size.
>The patch description is thus misleading. It also fails to explain
>this change ... probably because UL is C-A7 ?

Will consider to split this part into a single patch, and fix in V2.

>
>>  #define CONFIG_SYS_CACHELINE_SIZE	32
>> +#endif
>[...]
>
>Best regards,
>Marek Vasut

Regards,
Peng
diff mbox

Patch

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 35a324c..d78daac 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -9,7 +9,11 @@ 
 
 #define ARCH_MXC
 
+#ifdef CONFIG_MX6UL
+#define CONFIG_SYS_CACHELINE_SIZE	64
+#else
 #define CONFIG_SYS_CACHELINE_SIZE	32
+#endif
 
 #define ROMCP_ARB_BASE_ADDR             0x00000000
 #define ROMCP_ARB_END_ADDR              0x000FFFFF
@@ -19,7 +23,7 @@ 
 #define GPU_2D_ARB_END_ADDR             0x02203FFF
 #define OPENVG_ARB_BASE_ADDR            0x02204000
 #define OPENVG_ARB_END_ADDR             0x02207FFF
-#elif CONFIG_MX6SX
+#elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
 #define CAAM_ARB_BASE_ADDR              0x00100000
 #define CAAM_ARB_END_ADDR               0x00107FFF
 #define GPU_ARB_BASE_ADDR               0x01800000
@@ -28,10 +32,6 @@ 
 #define APBH_DMA_ARB_END_ADDR           0x0180BFFF
 #define M4_BOOTROM_BASE_ADDR			0x007F8000
 
-#define MXS_APBH_BASE			APBH_DMA_ARB_BASE_ADDR
-#define MXS_GPMI_BASE			(APBH_DMA_ARB_BASE_ADDR + 0x02000)
-#define MXS_BCH_BASE			(APBH_DMA_ARB_BASE_ADDR + 0x04000)
-
 #else
 #define CAAM_ARB_BASE_ADDR              0x00100000
 #define CAAM_ARB_END_ADDR               0x00103FFF
@@ -52,13 +52,13 @@ 
 #define MXS_BCH_BASE			(APBH_DMA_ARB_BASE_ADDR + 0x04000)
 
 /* GPV - PL301 configuration ports */
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
 #define GPV2_BASE_ADDR                  0x00D00000
 #else
 #define GPV2_BASE_ADDR			0x00200000
 #endif
 
-#ifdef CONFIG_MX6SX
+#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
 #define GPV3_BASE_ADDR			0x00E00000
 #define GPV4_BASE_ADDR			0x00F00000
 #define GPV5_BASE_ADDR			0x01000000
@@ -96,6 +96,11 @@ 
 #define QSPI0_AMBA_END                 0x6FFFFFFF
 #define QSPI1_AMBA_BASE                0x70000000
 #define QSPI1_AMBA_END                 0x7FFFFFFF
+#elif defined(CONFIG_MX6UL)
+#define WEIM_ARB_BASE_ADDR              0x50000000
+#define WEIM_ARB_END_ADDR               0x57FFFFFF
+#define QSPI0_AMBA_BASE                 0x60000000
+#define QSPI0_AMBA_END                  0x6FFFFFFF
 #else
 #define SATA_ARB_BASE_ADDR              0x02200000
 #define SATA_ARB_END_ADDR               0x02203FFF
@@ -111,7 +116,7 @@ 
 #define WEIM_ARB_END_ADDR               0x0FFFFFFF
 #endif
 
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
 #define MMDC0_ARB_BASE_ADDR             0x80000000
 #define MMDC0_ARB_END_ADDR              0xFFFFFFFF
 #define MMDC1_ARB_BASE_ADDR             0xC0000000
@@ -179,8 +184,13 @@ 
 #define GPIO3_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x24000)
 #define GPIO4_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x28000)
 #define GPIO5_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x2C000)
+#ifdef CONFIG_MX6UL
+#define SNVS_LP_BASE_ADDR           (AIPS1_OFF_BASE_ADDR + 0x30000)
+#define ENET2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x34000)
+#else
 #define GPIO6_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x30000)
 #define GPIO7_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x34000)
+#endif
 #define KPP_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x38000)
 #define WDOG1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x3C000)
 #define WDOG2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x40000)
@@ -249,6 +259,12 @@ 
 #define WEIM_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x38000)
 #define OCOTP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x3C000)
 #define CSU_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x40000)
+#ifdef CONFIG_MX6UL
+#define CSI_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x44000)
+#define LCDIF1_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x48000)
+#define LCDIF2_BASE_ADDR            LCDIF1_BASE_ADDR
+#define PXP_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x4C000)
+#else
 #define IP2APB_PERFMON1_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x44000)
 #define IP2APB_PERFMON2_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x48000)
 #ifdef CONFIG_MX6SX
@@ -256,19 +272,23 @@ 
 #else
 #define IP2APB_PERFMON3_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x4C000)
 #endif
+#endif
 #define IP2APB_TZASC1_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x50000)
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_MX6UL
+#define SYSCNT_RD_IPS_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x54000)
+#define SYSCNT_CMP_IPS_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x58000)
+#define SYSCNT_CTRL_IPS_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x5C000)
+#define SCTR_BASE_ADDR              SYSCNT_CTRL_IPS_BASE_ADDR
+#define QSPI0_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
+#define WDOG3_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x64000)
+#elif defined(CONFIG_MX6SX)
 #define SAI1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x54000)
-#else
-#define IP2APB_TZASC2_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x54000)
-#endif
 #define AUDMUX_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x58000)
-#define AUDMUX_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x58000)
-#ifdef CONFIG_MX6SX
 #define SAI2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x5C000)
 #define QSPI0_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
 #define QSPI1_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x64000)
 #else
+#define IP2APB_TZASC2_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x54000)
 #define MIPI_CSI2_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x5C000)
 #define MIPI_DSI_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x60000)
 #define VDOA_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x64000)
@@ -313,7 +333,7 @@ 
 #define CHIP_REV_1_2                 0x12
 #define CHIP_REV_1_5                 0x15
 #define CHIP_REV_2_0                 0x20
-#ifndef CONFIG_MX6SX
+#if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
 #define IRAM_SIZE                    0x00040000
 #else
 #define IRAM_SIZE                    0x00020000
@@ -451,7 +471,7 @@  struct src {
 
 
 struct iomuxc {
-#ifdef CONFIG_MX6SX
+#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
 	u8 reserved[0x4000];
 #endif
 	u32 gpr[14];
@@ -577,7 +597,7 @@  struct cspi_regs {
 #define MXC_CSPICON_POL		4  /* SCLK polarity */
 #define MXC_CSPICON_SSPOL	12 /* SS polarity */
 #define MXC_CSPICON_CTL		20 /* inactive state of SCLK */
-#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL)
+#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL)
 #define MXC_SPI_BASE_ADDRESSES \
 	ECSPI1_BASE_ADDR, \
 	ECSPI2_BASE_ADDR, \
@@ -661,7 +681,7 @@  struct fuse_bank1_regs {
 	u32	rsvd7[3];
 };
 
-#ifdef CONFIG_MX6SX
+#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
 struct fuse_bank4_regs {
 	u32 sjc_resp_low;
 	u32 rsvd0[3];
@@ -674,7 +694,9 @@  struct fuse_bank4_regs {
 	u32 mac_addr2;
 	u32 rsvd4[7];
 	u32 gp1;
-	u32 rsvd5[7];
+	u32 rsvd5[3];
+	u32 gp2;
+	u32 rsvd6[3];
 };
 #else
 struct fuse_bank4_regs {