| Message ID | 1435610957-24235-11-git-send-email-vikas.manocha@st.com |
|---|---|
| State | Superseded |
| Delegated to: | Jagannadha Sutradharudu Teki |
| Headers | show |
On 30 June 2015 at 02:19, Vikas Manocha <vikas.manocha@st.com> wrote: > This patch adds the device tree binding doc for the cadence qspi controller & > also removes the not needed properties from the device trees using this > controller. > > Signed-off-by: Vikas Manocha <vikas.manocha@st.com> > --- > > Changes in v3: added new > > arch/arm/dts/socfpga.dtsi | 3 --- > arch/arm/dts/socfpga_cyclone5_socrates.dts | 1 - > arch/arm/dts/stv0991.dts | 4 ---- > doc/device-tree-bindings/spi/spi-cadence.txt | 28 ++++++++++++++++++++++++++ > 4 files changed, 28 insertions(+), 8 deletions(-) > create mode 100644 doc/device-tree-bindings/spi/spi-cadence.txt > > diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi > index 9b12420..35e6561 100644 > --- a/arch/arm/dts/socfpga.dtsi > +++ b/arch/arm/dts/socfpga.dtsi > @@ -636,9 +636,6 @@ > <0xffa00000 0x1000>; > interrupts = <0 151 4>; > clocks = <&qspi_clk>; > - ext-decoder = <0>; /* external decoder */ > - num-cs = <4>; > - fifo-depth = <128>; > sram-size = <128>; > bus-num = <2>; > status = "disabled"; > diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts > index ea30483..557787b 100644 > --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts > +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts > @@ -56,7 +56,6 @@ > m25p,fast-read; > page-size = <256>; > block-size = <16>; /* 2^16, 64KB */ > - read-delay = <4>; /* delay value in read data capture register */ > tshsl-ns = <50>; > tsd2d-ns = <50>; > tchsh-ns = <4>; > diff --git a/arch/arm/dts/stv0991.dts b/arch/arm/dts/stv0991.dts > index 556df82..601148e 100644 > --- a/arch/arm/dts/stv0991.dts > +++ b/arch/arm/dts/stv0991.dts > @@ -32,9 +32,6 @@ > reg = <0x80203000 0x100>, > <0x40000000 0x1000000>; > clocks = <3750000>; > - ext-decoder = <0>; /* external decoder */ > - num-cs = <4>; > - fifo-depth = <256>; > sram-size = <256>; > bus-num = <0>; > status = "okay"; > @@ -48,7 +45,6 @@ > m25p,fast-read; > page-size = <256>; > block-size = <16>; /* 2^16, 64KB */ > - read-delay = <4>; /* delay value in read data capture register */ > tshsl-ns = <50>; > tsd2d-ns = <50>; > tchsh-ns = <4>; > diff --git a/doc/device-tree-bindings/spi/spi-cadence.txt b/doc/device-tree-bindings/spi/spi-cadence.txt > new file mode 100644 > index 0000000..c1e2233 > --- /dev/null > +++ b/doc/device-tree-bindings/spi/spi-cadence.txt > @@ -0,0 +1,28 @@ > +Cadence QSPI controller device tree bindings > +-------------------------------------------- > + > +Required properties: > +- compatible : should be "cadence,qspi". > +- reg : 1.Physical base address and size of SPI registers map. > + 2. Physical base address & size of NOR Flash. > +- clocks : Clock phandles (see clock bindings for details). > +- sram-size : spi controller sram size. ? bus-num > +- status : enable in requried dts. > + > +connected flash properties > +-------------------------- > + > +- spi-max-frequency : Max supported spi frequency. > +- page-size : Flash page size. > +- block-size : Flash memory block size. > +- tshsl-ns : Added delay in master reference clocks (ref_clk) for > + the length that the master mode chip select outputs > + are de-asserted between transactions. > +- tsd2d-ns : Delay in master reference clocks (ref_clk) between one > + chip select being de-activated and the activation of > + another. > +- tchsh-ns : Delay in master reference clocks between last bit of > + current transaction and de-asserting the device chip > + select (n_ss_out). > +- tslch-ns : Delay in master reference clocks between setting > + n_ss_out low and first bit transfer > -- thanks!
Thanks Jagan, > -----Original Message----- > From: Jagan Teki [mailto:jteki@openedev.com] > Sent: Monday, June 29, 2015 11:29 PM > To: Vikas MANOCHA > Cc: u-boot@lists.denx.de; Stefan Roese > Subject: Re: [U-Boot] [v3 10/10] spi: cadence_qspi: add device tree binding > doc > > On 30 June 2015 at 02:19, Vikas Manocha <vikas.manocha@st.com> wrote: > > This patch adds the device tree binding doc for the cadence qspi > > controller & also removes the not needed properties from the device > > trees using this controller. > > > > Signed-off-by: Vikas Manocha <vikas.manocha@st.com> > > --- > > > > Changes in v3: added new > > > > arch/arm/dts/socfpga.dtsi | 3 --- > > arch/arm/dts/socfpga_cyclone5_socrates.dts | 1 - > > arch/arm/dts/stv0991.dts | 4 ---- > > doc/device-tree-bindings/spi/spi-cadence.txt | 28 > ++++++++++++++++++++++++++ > > 4 files changed, 28 insertions(+), 8 deletions(-) create mode 100644 > > doc/device-tree-bindings/spi/spi-cadence.txt > > > > diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi > > index 9b12420..35e6561 100644 > > --- a/arch/arm/dts/socfpga.dtsi > > +++ b/arch/arm/dts/socfpga.dtsi > > @@ -636,9 +636,6 @@ > > <0xffa00000 0x1000>; > > interrupts = <0 151 4>; > > clocks = <&qspi_clk>; > > - ext-decoder = <0>; /* external decoder */ > > - num-cs = <4>; > > - fifo-depth = <128>; > > sram-size = <128>; > > bus-num = <2>; > > status = "disabled"; diff --git > > a/arch/arm/dts/socfpga_cyclone5_socrates.dts > > b/arch/arm/dts/socfpga_cyclone5_socrates.dts > > index ea30483..557787b 100644 > > --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts > > +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts > > @@ -56,7 +56,6 @@ > > m25p,fast-read; > > page-size = <256>; > > block-size = <16>; /* 2^16, 64KB */ > > - read-delay = <4>; /* delay value in read data capture register */ > > tshsl-ns = <50>; > > tsd2d-ns = <50>; > > tchsh-ns = <4>; > > diff --git a/arch/arm/dts/stv0991.dts b/arch/arm/dts/stv0991.dts index > > 556df82..601148e 100644 > > --- a/arch/arm/dts/stv0991.dts > > +++ b/arch/arm/dts/stv0991.dts > > @@ -32,9 +32,6 @@ > > reg = <0x80203000 0x100>, > > <0x40000000 0x1000000>; > > clocks = <3750000>; > > - ext-decoder = <0>; /* external decoder */ > > - num-cs = <4>; > > - fifo-depth = <256>; > > sram-size = <256>; > > bus-num = <0>; > > status = "okay"; @@ -48,7 +45,6 @@ > > m25p,fast-read; > > page-size = <256>; > > block-size = <16>; /* 2^16, 64KB */ > > - read-delay = <4>; /* delay value in read data capture > register */ > > tshsl-ns = <50>; > > tsd2d-ns = <50>; > > tchsh-ns = <4>; diff --git > > a/doc/device-tree-bindings/spi/spi-cadence.txt > > b/doc/device-tree-bindings/spi/spi-cadence.txt > > new file mode 100644 > > index 0000000..c1e2233 > > --- /dev/null > > +++ b/doc/device-tree-bindings/spi/spi-cadence.txt > > @@ -0,0 +1,28 @@ > > +Cadence QSPI controller device tree bindings > > +-------------------------------------------- > > + > > +Required properties: > > +- compatible : should be "cadence,qspi". > > +- reg : 1.Physical base address and size of SPI registers map. > > + 2. Physical base address & size of NOR Flash. > > +- clocks : Clock phandles (see clock bindings for details). > > +- sram-size : spi controller sram size. > > ? bus-num It is not being used in the cadence_qspi driver but used on socfpga arch to distinguish between different spi peripherals. Stefan, Can you please comment about it. It is ok to remove it from "arch/arm/dts/socfpga.dtsi" Rgds, Vikas > > > +- status : enable in requried dts. > > + > > +connected flash properties > > +-------------------------- > > + > > +- spi-max-frequency : Max supported spi frequency. > > +- page-size : Flash page size. > > +- block-size : Flash memory block size. > > +- tshsl-ns : Added delay in master reference clocks (ref_clk) for > > + the length that the master mode chip select outputs > > + are de-asserted between transactions. > > +- tsd2d-ns : Delay in master reference clocks (ref_clk) between one > > + chip select being de-activated and the activation of > > + another. > > +- tchsh-ns : Delay in master reference clocks between last bit of > > + current transaction and de-asserting the device chip > > + select (n_ss_out). > > +- tslch-ns : Delay in master reference clocks between setting > > + n_ss_out low and first bit transfer > > -- > > thanks! > -- > Jagan | openedev.
Hi Vikas, On 01.07.2015 00:57, Vikas MANOCHA wrote: >>> +Cadence QSPI controller device tree bindings >>> +-------------------------------------------- >>> + >>> +Required properties: >>> +- compatible : should be "cadence,qspi". >>> +- reg : 1.Physical base address and size of SPI registers map. >>> + 2. Physical base address & size of NOR Flash. >>> +- clocks : Clock phandles (see clock bindings for details). >>> +- sram-size : spi controller sram size. >> >> ? bus-num > > It is not being used in the cadence_qspi driver but used on socfpga > arch to distinguish between different spi peripherals. > > Stefan, > Can you please comment about it. It is ok to remove it from > "arch/arm/dts/socfpga.dtsi" Not sure. Why do we need to remove it? I would prefer to keep it as its know to work this way. BTW: We need to re-sync with the Linux Cadence QSPI NOR driver at some time. At least in regard to the device-tree properties. The driver has been posted for quite some time now. And I hope it will be accepted soon. And as you can see from [1] the bindings / properties differ a bit from our currently used ones. So once this driver is accepted in kernel.org, we need to re-sync the bindings / dts files again. Thanks, Stefan [1] http://permalink.gmane.org/gmane.linux.drivers.mtd/58159
Hi Jagan, > -----Original Message----- > From: Stefan Roese [mailto:sr@denx.de] > Sent: Thursday, July 02, 2015 3:12 AM > To: Vikas MANOCHA; Jagan Teki > Cc: u-boot@lists.denx.de > Subject: Re: [U-Boot] [v3 10/10] spi: cadence_qspi: add device tree binding > doc > > Hi Vikas, > > On 01.07.2015 00:57, Vikas MANOCHA wrote: > >>> +Cadence QSPI controller device tree bindings > >>> +-------------------------------------------- > >>> + > >>> +Required properties: > >>> +- compatible : should be "cadence,qspi". > >>> +- reg : 1.Physical base address and size of SPI registers map. > >>> + 2. Physical base address & size of NOR Flash. > >>> +- clocks : Clock phandles (see clock bindings for details). > >>> +- sram-size : spi controller sram size. > >> > >> ? bus-num > > > > It is not being used in the cadence_qspi driver but used on socfpga > > arch to distinguish between different spi peripherals. > > > > Stefan, > > Can you please comment about it. It is ok to remove it from > > "arch/arm/dts/socfpga.dtsi" > > Not sure. Why do we need to remove it? I would prefer to keep it as its know > to work this way. > > BTW: We need to re-sync with the Linux Cadence QSPI NOR driver at some > time. At least in regard to the device-tree properties. The driver has been > posted for quite some time now. And I hope it will be accepted soon. And as > you can see from [1] the bindings / properties differ a bit from our currently > used ones. So once this driver is accepted in kernel.org, we need to re-sync > the bindings / dts files again. Jagan, do you agree not to remove it ? Rgds, Vikas > > Thanks, > Stefan > > [1] http://permalink.gmane.org/gmane.linux.drivers.mtd/58159
On 2 July 2015 at 23:12, Vikas MANOCHA <vikas.manocha@st.com> wrote: > Hi Jagan, > >> -----Original Message----- >> From: Stefan Roese [mailto:sr@denx.de] >> Sent: Thursday, July 02, 2015 3:12 AM >> To: Vikas MANOCHA; Jagan Teki >> Cc: u-boot@lists.denx.de >> Subject: Re: [U-Boot] [v3 10/10] spi: cadence_qspi: add device tree binding >> doc >> >> Hi Vikas, >> >> On 01.07.2015 00:57, Vikas MANOCHA wrote: >> >>> +Cadence QSPI controller device tree bindings >> >>> +-------------------------------------------- >> >>> + >> >>> +Required properties: >> >>> +- compatible : should be "cadence,qspi". >> >>> +- reg : 1.Physical base address and size of SPI registers map. >> >>> + 2. Physical base address & size of NOR Flash. >> >>> +- clocks : Clock phandles (see clock bindings for details). >> >>> +- sram-size : spi controller sram size. >> >> >> >> ? bus-num >> > >> > It is not being used in the cadence_qspi driver but used on socfpga >> > arch to distinguish between different spi peripherals. >> > >> > Stefan, >> > Can you please comment about it. It is ok to remove it from >> > "arch/arm/dts/socfpga.dtsi" >> >> Not sure. Why do we need to remove it? I would prefer to keep it as its know >> to work this way. >> >> BTW: We need to re-sync with the Linux Cadence QSPI NOR driver at some >> time. At least in regard to the device-tree properties. The driver has been >> posted for quite some time now. And I hope it will be accepted soon. And as >> you can see from [1] the bindings / properties differ a bit from our currently >> used ones. So once this driver is accepted in kernel.org, we need to re-sync >> the bindings / dts files again. > > Jagan, do you agree not to remove it ? Yes, but one think you can do is just add what ever nodes required on your dts and document the same - don't touch dtsi. thanks!
Thanks Jagan, > -----Original Message----- > From: Jagan Teki [mailto:jteki@openedev.com] > Sent: Thursday, July 02, 2015 10:49 AM > To: Vikas MANOCHA > Cc: Stefan Roese; u-boot@lists.denx.de > Subject: Re: [U-Boot] [v3 10/10] spi: cadence_qspi: add device tree binding > doc > > On 2 July 2015 at 23:12, Vikas MANOCHA <vikas.manocha@st.com> wrote: > > Hi Jagan, > > > >> -----Original Message----- > >> From: Stefan Roese [mailto:sr@denx.de] > >> Sent: Thursday, July 02, 2015 3:12 AM > >> To: Vikas MANOCHA; Jagan Teki > >> Cc: u-boot@lists.denx.de > >> Subject: Re: [U-Boot] [v3 10/10] spi: cadence_qspi: add device tree > >> binding doc > >> > >> Hi Vikas, > >> > >> On 01.07.2015 00:57, Vikas MANOCHA wrote: > >> >>> +Cadence QSPI controller device tree bindings > >> >>> +-------------------------------------------- > >> >>> + > >> >>> +Required properties: > >> >>> +- compatible : should be "cadence,qspi". > >> >>> +- reg : 1.Physical base address and size of SPI registers map. > >> >>> + 2. Physical base address & size of NOR Flash. > >> >>> +- clocks : Clock phandles (see clock bindings for details). > >> >>> +- sram-size : spi controller sram size. > >> >> > >> >> ? bus-num > >> > > >> > It is not being used in the cadence_qspi driver but used on socfpga > >> > arch to distinguish between different spi peripherals. > >> > > >> > Stefan, > >> > Can you please comment about it. It is ok to remove it from > >> > "arch/arm/dts/socfpga.dtsi" > >> > >> Not sure. Why do we need to remove it? I would prefer to keep it as > >> its know to work this way. > >> > >> BTW: We need to re-sync with the Linux Cadence QSPI NOR driver at > >> some time. At least in regard to the device-tree properties. The > >> driver has been posted for quite some time now. And I hope it will be > >> accepted soon. And as you can see from [1] the bindings / properties > >> differ a bit from our currently used ones. So once this driver is > >> accepted in kernel.org, we need to re-sync the bindings / dts files again. > > > > Jagan, do you agree not to remove it ? > > Yes, but one think you can do is just add what ever nodes required on your > dts and document the same - don't touch dtsi. Makes sense, will do it. Rgds, Vikas > > thanks! > -- > Jagan | openedev.
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index 9b12420..35e6561 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -636,9 +636,6 @@ <0xffa00000 0x1000>; interrupts = <0 151 4>; clocks = <&qspi_clk>; - ext-decoder = <0>; /* external decoder */ - num-cs = <4>; - fifo-depth = <128>; sram-size = <128>; bus-num = <2>; status = "disabled"; diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts index ea30483..557787b 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -56,7 +56,6 @@ m25p,fast-read; page-size = <256>; block-size = <16>; /* 2^16, 64KB */ - read-delay = <4>; /* delay value in read data capture register */ tshsl-ns = <50>; tsd2d-ns = <50>; tchsh-ns = <4>; diff --git a/arch/arm/dts/stv0991.dts b/arch/arm/dts/stv0991.dts index 556df82..601148e 100644 --- a/arch/arm/dts/stv0991.dts +++ b/arch/arm/dts/stv0991.dts @@ -32,9 +32,6 @@ reg = <0x80203000 0x100>, <0x40000000 0x1000000>; clocks = <3750000>; - ext-decoder = <0>; /* external decoder */ - num-cs = <4>; - fifo-depth = <256>; sram-size = <256>; bus-num = <0>; status = "okay"; @@ -48,7 +45,6 @@ m25p,fast-read; page-size = <256>; block-size = <16>; /* 2^16, 64KB */ - read-delay = <4>; /* delay value in read data capture register */ tshsl-ns = <50>; tsd2d-ns = <50>; tchsh-ns = <4>; diff --git a/doc/device-tree-bindings/spi/spi-cadence.txt b/doc/device-tree-bindings/spi/spi-cadence.txt new file mode 100644 index 0000000..c1e2233 --- /dev/null +++ b/doc/device-tree-bindings/spi/spi-cadence.txt @@ -0,0 +1,28 @@ +Cadence QSPI controller device tree bindings +-------------------------------------------- + +Required properties: +- compatible : should be "cadence,qspi". +- reg : 1.Physical base address and size of SPI registers map. + 2. Physical base address & size of NOR Flash. +- clocks : Clock phandles (see clock bindings for details). +- sram-size : spi controller sram size. +- status : enable in requried dts. + +connected flash properties +-------------------------- + +- spi-max-frequency : Max supported spi frequency. +- page-size : Flash page size. +- block-size : Flash memory block size. +- tshsl-ns : Added delay in master reference clocks (ref_clk) for + the length that the master mode chip select outputs + are de-asserted between transactions. +- tsd2d-ns : Delay in master reference clocks (ref_clk) between one + chip select being de-activated and the activation of + another. +- tchsh-ns : Delay in master reference clocks between last bit of + current transaction and de-asserting the device chip + select (n_ss_out). +- tslch-ns : Delay in master reference clocks between setting + n_ss_out low and first bit transfer
This patch adds the device tree binding doc for the cadence qspi controller & also removes the not needed properties from the device trees using this controller. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> --- Changes in v3: added new arch/arm/dts/socfpga.dtsi | 3 --- arch/arm/dts/socfpga_cyclone5_socrates.dts | 1 - arch/arm/dts/stv0991.dts | 4 ---- doc/device-tree-bindings/spi/spi-cadence.txt | 28 ++++++++++++++++++++++++++ 4 files changed, 28 insertions(+), 8 deletions(-) create mode 100644 doc/device-tree-bindings/spi/spi-cadence.txt