| Message ID | n99bng21svt.fsf@arm.com |
|---|---|
| State | New |
| Headers | show |
Jiong Wang writes: > Marcus Shawcroft writes: > >> On 26 June 2015 at 10:32, Jiong Wang <jiong.wang@arm.com> wrote: >>> >>> This patch respin https://gcc.gnu.org/ml/gcc-patches/2015-05/msg01804.html. >>> >>> A new symbol classification "SYMBOL_SMALL_GOT_28K" added to represent symbol >>> which needs go through GOT table and it's under -fpic/-mcmodel-small. the "_28K" >>> suffix can reflect the symbol's attribute better, and by introducing this new >>> symbol type, we could avoid checking aarch64_cmodel at some extent >>> though still needs the check somewhere. >>> >>> All other code logic not changed. >>> >>> OK for trunk? >>> >>> Thanks. >>> >>> 2015-06-26 Jiong. Wang <jiong.wang@arm.com> >>> >>> gcc/ >>> * config/aarch64/aarch64-protos.h (aarch64_symbol_type): New type >>> SYMBOL_SMALL_GOT_28K. >>> * config/aarch64/aarch64.md: (ldr_got_small_<mode>): Support new GOT >>> relocation modifiers. >>> (unspec): New enum "UNSPEC_GOTMALLPIC28K. >>> (ldr_got_small_28k_<mode>): New. >>> (ldr_got_small_28k_sidi): New. >>> * config/aarch64/iterators.md (got_modifier): New mode iterator. >>> * config/aarch64/aarch64-otps.h (aarch64_code_model): New model. >>> * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Support >>> SYMBOL_SMALL_GOT_28K. >>> (aarch64_rtx_costs): Add costs for new instruction sequences. >>> (initialize_aarch64_code_model): Initialize new model. >>> (aarch64_classify_symbol): Recognize new model and new symbol classification. >>> (aarch64_asm_preferred_eh_data_format): Support new model. >>> (aarch64_load_symref_appropriately): Generate new instruction >>> sequences for -fpic. >>> (TARGET_USE_PSEUDO_PIC_REG): New definition. >>> (aarch64_use_pseudo_pic_reg): New function. >>> >>> gcc/testsuite/ >>> * gcc.target/aarch64/pic-small.c: New testcase. >> >> >> OK, Thanks Jiong. Could you prepare a NEWS entry for this change? >> Cheers >> /Marcus > > How about this one? > > 2015-06-26 Jiong Wang <jiong.wang@arm.com> > > wwwdocs/ > * htdocs/gcc-6/changes.html (AArch64): Document -fpic for small > model. Ping. -fpic patch for AArch64 has been committed, this is the documentation counterpart which needs approval. Thanks.
On Fri, Jun 26, 2015 at 02:45:39PM +0100, Jiong Wang wrote: > > Marcus Shawcroft writes: > > 2015-06-26 Jiong Wang <jiong.wang@arm.com> > > wwwdocs/ > * htdocs/gcc-6/changes.html (AArch64): Document -fpic for small model. > > Index: gcc-6/changes.html > =================================================================== > RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-6/changes.html,v > retrieving revision 1.12 > diff -u -r1.12 changes.html > --- gcc-6/changes.html 16 Jun 2015 08:48:02 -0000 1.12 > +++ gcc-6/changes.html 26 Jun 2015 13:30:05 -0000 > @@ -90,6 +90,15 @@ > If GCC is unable to detect the host CPU these options have no effect. > </li> > </ul> > + <ul> This should be a new <li> (list item) in the above <ul> (unordered list), rather than a new <ul>. > + <li> > + <code>-fpic</code> is now supported on AArch64 for small memory > + model. In invoke.texi we describe -mcmodel as the "small code model" rather than as a "memory model". How about rewording this as so: <code>-fpic</code> is now supported by the AArch64 target when generating code for the small code model (<code>-mcmodel=small</code>). > Compared with <code>-fPIC</code>, <code>-fpic</code> > + will guide GCC to generate more efficient position independent > + instruction sequences when accessing global objects and > + 28KiB/15KiB global offset table size supported under ILP64/32. I'm not sure this part is needed, the difference between -fpic and -fPIC is already covered by invoke.texi. If you do want to include this text, I might try rewriting it as: <code>-fpic</code> generates position-independent code which accesses all constant addresses through a global offset table (GOT). For AArch64, the size of the GOT is limited to 28KiB under the LP64 SysV ABI, and 15KiB under the ILP32 SysV ABI. As I was looking in invoke.texi, do we want to document the limits on our GOT size there as other targets have? "These maximums are 8k on the SPARC and 32k on the m68k and RS/6000. The x86 has no such limit." Thanks, James
Index: gcc-6/changes.html =================================================================== RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-6/changes.html,v retrieving revision 1.12 diff -u -r1.12 changes.html --- gcc-6/changes.html 16 Jun 2015 08:48:02 -0000 1.12 +++ gcc-6/changes.html 26 Jun 2015 13:30:05 -0000 @@ -90,6 +90,15 @@ If GCC is unable to detect the host CPU these options have no effect. </li> </ul> + <ul> + <li> + <code>-fpic</code> is now supported on AArch64 for small memory + model. Compared with <code>-fPIC</code>, <code>-fpic</code> + will guide GCC to generate more efficient position independent + instruction sequences when accessing global objects and + 28KiB/15KiB global offset table size supported under ILP64/32. + </li> + </ul> <!-- <h3 id="arm">ARM</h3> --> <!-- <h3 id="avr">AVR</h3> -->