diff mbox

[PULL,06/20] target-mips: fix {RD, WR}PGPR in microMIPS

Message ID 1435314324-8755-7-git-send-email-leon.alrae@imgtec.com
State New
Headers show

Commit Message

Leon Alrae June 26, 2015, 10:25 a.m. UTC 
From: Yongbok Kim <yongbok.kim@imgtec.com>

rt, rs were swapped

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 target-mips/translate.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
diff mbox

Patch

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 8547e2d..02c2523 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -13001,12 +13001,12 @@  static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
         case RDPGPR:
             check_cp0_enabled(ctx);
             check_insn(ctx, ISA_MIPS32R2);
-            gen_load_srsgpr(rt, rs);
+            gen_load_srsgpr(rs, rt);
             break;
         case WRPGPR:
             check_cp0_enabled(ctx);
             check_insn(ctx, ISA_MIPS32R2);
-            gen_store_srsgpr(rt, rs);
+            gen_store_srsgpr(rs, rt);
             break;
         default:
             goto pool32axf_invalid;