From patchwork Thu Jun 25 22:43:07 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 488582 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 095361400A0 for ; Fri, 26 Jun 2015 08:43:13 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751576AbbFYWnM (ORCPT ); Thu, 25 Jun 2015 18:43:12 -0400 Received: from mail-la0-f46.google.com ([209.85.215.46]:36579 "EHLO mail-la0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751379AbbFYWnL (ORCPT ); Thu, 25 Jun 2015 18:43:11 -0400 Received: by lacny3 with SMTP id ny3so53464326lac.3 for ; Thu, 25 Jun 2015 15:43:09 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id:organization :user-agent:in-reply-to:references:mime-version :content-transfer-encoding:content-type; bh=T+pd43dw7VOYLpkJQ1fX32QFv+evnQE1D4+a5qxXN1s=; b=ljuaWCkTb+Z3wJpIff9EO/QJK8dJaV+YdTNeU0x0CTTiRarXul5Oa9LBWeafgPGrfY WAYmyNseFRdP4IIDExv6MxfYYR5b0gf10OVSkmQTL5F3UgvDzKmCpy9cTqUdObIwhC0z KSdMthc/Oja7cdEDY//OZwUg2v+F0P1cwe48MpmDxT8KS6O4hwmH1SBj48M5mb0WnDfB Op3LRpdND2CTVtl7dpk2OkhmLVM0SVxQ1VDjkwr61yJxaZ+fFro5vCSh+kadZXcadUT3 1Hn1hKf4eizCxGTo6VgP8/bsMPmKbglXtxJJtHBsWPGdJ3I+DhyA/vGENfD5C0K6iUWy 81SA== X-Gm-Message-State: ALoCoQlnmrN8qv8oelUzCcV8WZiSqmhAxGBkIYTHSMXnGeGv7ZTZAqFWjmwsJarKIzdJ1f0FofBF X-Received: by 10.112.25.10 with SMTP id y10mr46702842lbf.61.1435272189681; Thu, 25 Jun 2015 15:43:09 -0700 (PDT) Received: from wasted.cogentembedded.com (ppp85-141-193-152.pppoe.mtu-net.ru. [85.141.193.152]) by mx.google.com with ESMTPSA id yf5sm7533628lab.1.2015.06.25.15.43.08 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Jun 2015 15:43:08 -0700 (PDT) From: Sergei Shtylyov To: linus.walleij@linaro.org, linux-sh@vger.kernel.org, laurent.pinchart@ideasonboard.com, linux-gpio@vger.kernel.org Subject: [PATCH v3 3/3] sh-pfc: r8a7791: remove non-existing GPIO pins Date: Fri, 26 Jun 2015 01:43:07 +0300 Message-ID: <1503001.TnFHhSFjY8@wasted.cogentembedded.com> Organization: Cogent Embedded Inc. User-Agent: KMail/4.14.7 (Linux/4.0.5-200.fc21.x86_64; KDE/4.14.9; x86_64; ; ) In-Reply-To: <1460630.GxHT4lRd7u@wasted.cogentembedded.com> References: <1460630.GxHT4lRd7u@wasted.cogentembedded.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Laurent Pinchart GPIO banks 1 and 7 are missing pins 26 to 31. Remove them. Signed-off-by: Laurent Pinchart Signed-off-by: Sergei Shtylyov Tested-by: Geert Uytterhoeven --- Changes in version 2: - renamed the patch. drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Index: linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7791.c =================================================================== --- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -14,15 +14,30 @@ #include "core.h" #include "sh_pfc.h" +#define PORT_GP_26(bank, fn, sfx) \ + PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ + PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ + PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ + PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ + PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ + PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ + PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ + PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ + PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ + PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ + PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ + PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ + PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx) + #define CPU_ALL_PORT(fn, sfx) \ PORT_GP_32(0, fn, sfx), \ - PORT_GP_32(1, fn, sfx), \ + PORT_GP_26(1, fn, sfx), \ PORT_GP_32(2, fn, sfx), \ PORT_GP_32(3, fn, sfx), \ PORT_GP_32(4, fn, sfx), \ PORT_GP_32(5, fn, sfx), \ PORT_GP_32(6, fn, sfx), \ - PORT_GP_32(7, fn, sfx) + PORT_GP_26(7, fn, sfx) enum { PINMUX_RESERVED = 0,