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[v4,02/15] target-mips: add microMIPS TLBINV, TLBINVF

Message ID 1435188267-54510-3-git-send-email-yongbok.kim@imgtec.com
State New
Headers show

Commit Message

Yongbok Kim June 24, 2015, 11:24 p.m. UTC 
Add microMIPS TLBINV, TLBINVF

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
---
 target-mips/translate.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)
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Patch

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 97b74ba..963ff8b 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -12233,6 +12233,8 @@  enum {
     TLBR = 0x1,
     TLBWI = 0x2,
     TLBWR = 0x3,
+    TLBINV = 0x4,
+    TLBINVF = 0x5,
     WAIT = 0x9,
     IRET = 0xd,
     DERET = 0xe,
@@ -13017,6 +13019,12 @@  static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
         case TLBWR:
             mips32_op = OPC_TLBWR;
             goto do_cp0;
+        case TLBINV:
+            mips32_op = OPC_TLBINV;
+            goto do_cp0;
+        case TLBINVF:
+            mips32_op = OPC_TLBINVF;
+            goto do_cp0;
         case WAIT:
             mips32_op = OPC_WAIT;
             goto do_cp0;