@@ -414,7 +414,7 @@
(unspec:<non_vec> [(match_operand:V_HW_64 0 "register_operand" "v")
(match_dup 3)] UNSPEC_VEC_EXTRACT))]
"TARGET_VX && !TARGET_64BIT"
- "vsce<V_HW_64:gf>\t%v0,%O2(%v1,%R2),%3"
+ "vsce<V_HW_64:bhfgq>\t%v0,%O2(%v1,%R2),%3"
[(set_attr "op_type" "VRV")])
; Element size and target adress size is the same
@@ -428,7 +428,7 @@
(unspec:<non_vec> [(match_operand:V_HW_32_64 0 "register_operand" "v")
(match_dup 3)] UNSPEC_VEC_EXTRACT))]
"TARGET_VX"
- "vsce<gf>\t%v0,%O2(%v1,%R2),%3"
+ "vsce<bhfgq>\t%v0,%O2(%v1,%R2),%3"
[(set_attr "op_type" "VRV")])
; Depending on the address size we have to expand a different pattern.
This fixes the mode attribute used in the vec scatter insn definitions. vec_scatter_element<mode>_<non_vec_int> and vec_scatter_element<V_HW_64:mode>_SI were using gf mode attribute which does not support vector modes. gcc/ChangeLog: * config/s390/vx-builtins.md ("vec_scatter_element<mode>_<non_vec_int>") ("vec_scatter_element<V_HW_64:mode>_SI"): Replace gf mode attribute with bhfgq. --- gcc/config/s390/vx-builtins.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)