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[U-Boot,2/5] sunxi: rsb: Enable R_PIO clock before configuring external pins

Message ID 1435060647-30648-3-git-send-email-wens@csie.org
State Accepted
Delegated to: Hans de Goede
Headers show

Commit Message

Chen-Yu Tsai June 23, 2015, 11:57 a.m. UTC
The original code was configuring the external pins after enabling
the R_PIO clock, which meant the configuration never made it to
the pin controller the first time in SPL.

Why this was working before is uncertain. Maybe the state was left
from a previous boot sequence, or RSB just happened to be the default
configuration. However with some A33 chips, SPL failed to configure
the PMIC. This was seen by me and Maxime on the Sinlinx SinA33 dev
board.

Reordering the calls fixed this.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 arch/arm/cpu/armv7/sunxi/rsb.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

Comments

Maxime Ripard June 23, 2015, 6:29 p.m. UTC | #1
On Tue, Jun 23, 2015 at 07:57:24PM +0800, Chen-Yu Tsai wrote:
> The original code was configuring the external pins after enabling
> the R_PIO clock, which meant the configuration never made it to
> the pin controller the first time in SPL.
> 
> Why this was working before is uncertain. Maybe the state was left
> from a previous boot sequence, or RSB just happened to be the default
> configuration. However with some A33 chips, SPL failed to configure
> the PMIC. This was seen by me and Maxime on the Sinlinx SinA33 dev
> board.
> 
> Reordering the calls fixed this.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> Cc: Maxime Ripard <maxime.ripard@free-electrons.com>

Tested-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Thanks!
Maxime
diff mbox

Patch

diff --git a/arch/arm/cpu/armv7/sunxi/rsb.c b/arch/arm/cpu/armv7/sunxi/rsb.c
index f115a9c..6fd11f1 100644
--- a/arch/arm/cpu/armv7/sunxi/rsb.c
+++ b/arch/arm/cpu/armv7/sunxi/rsb.c
@@ -60,11 +60,12 @@  int rsb_init(void)
 	struct sunxi_rsb_reg * const rsb =
 		(struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
 
-	rsb_cfg_io();
-
 	/* Enable RSB and PIO clk, and de-assert their resets */
 	prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
 
+	/* Setup external pins */
+	rsb_cfg_io();
+
 	writel(RSB_CTRL_SOFT_RST, &rsb->ctrl);
 	rsb_set_clk();