From patchwork Fri Jun 5 22:35:54 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 481582 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id AB31E14018C for ; Sat, 6 Jun 2015 08:35:59 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751745AbbFEWf7 (ORCPT ); Fri, 5 Jun 2015 18:35:59 -0400 Received: from mail-lb0-f170.google.com ([209.85.217.170]:32964 "EHLO mail-lb0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751877AbbFEWf6 (ORCPT ); Fri, 5 Jun 2015 18:35:58 -0400 Received: by lbcue7 with SMTP id ue7so53939857lbc.0 for ; Fri, 05 Jun 2015 15:35:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id:organization :user-agent:in-reply-to:references:mime-version :content-transfer-encoding:content-type; bh=wc2ZNmc9mp2/b3iFKPFRiNgPBtcRkUbsDkPNUsJgi1w=; b=c4sAA14GwXueklTFcN0NqLUdxe8ZorNRwdv8uyS18/dZfcTOo0GuyAzzOVGVB+v22e o7k6n7dFXlig2WWMbhxoxDF/07am/Fsu9HzMz+g5ZmfMUFfNGHGuBO1yWsclH5WXyhyU 89qiTFgnTFKkqThlq6SOZ4QrAVz+LdWdKmcGVN79lt/LgNlDdpjvqO0rRZGmj0Xk5dRD VXkjtAkDGPc0t6VUMWEkf9EDNPR7Zy0hQ5qqhgzohUutYsygtUtiOOeZAi2WtZ3R3qQK mI80GACpxSwENhKDmpJGAMCZJNKT96OpTwb4SP7Er8muhkfmq1erBQXR0ZZ1zwuFT/6T LJRQ== X-Gm-Message-State: ALoCoQkhWXFHqG7vGNsMHH4Y/lKH5XaywcqRKhi5mPst6aETW16CuQyHIi1CNREy2ybon1eM3NWV X-Received: by 10.152.184.101 with SMTP id et5mr5389385lac.43.1433543757208; Fri, 05 Jun 2015 15:35:57 -0700 (PDT) Received: from wasted.cogentembedded.com (ppp83-237-253-66.pppoe.mtu-net.ru. [83.237.253.66]) by mx.google.com with ESMTPSA id q1sm2092453lah.27.2015.06.05.15.35.55 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Jun 2015 15:35:56 -0700 (PDT) From: Sergei Shtylyov To: linus.walleij@linaro.org, linux-sh@vger.kernel.org, laurent.pinchart@ideasonboard.com, linux-gpio@vger.kernel.org Subject: [PATCH v5 2/3] sh-pfc: r8a7794: add MMCIF pin groups Date: Sat, 06 Jun 2015 01:35:54 +0300 Message-ID: <3463514.kOPJ22qAGq@wasted.cogentembedded.com> Organization: Cogent Embedded Inc. User-Agent: KMail/4.14.7 (Linux/3.19.8-100.fc20.x86_64; KDE/4.14.7; x86_64; ; ) In-Reply-To: <4547979.iqiS3iOv3s@wasted.cogentembedded.com> References: <4547979.iqiS3iOv3s@wasted.cogentembedded.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Shinobu Uehara Add MMCIF pin groups to R8A7794 PFC driver. Signed-off-by: Shinobu Uehara [Sergei: rebased, renamed, added changelog.] Signed-off-by: Sergei Shtylyov Acked-by: Laurent Pinchart --- Changes in version 5: - refreshed the patch; - added Laurent Pinchart's ACK. drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 46 +++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Index: linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7794.c =================================================================== --- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +++ linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7794.c @@ -1919,6 +1919,40 @@ static const unsigned int intc_irq9_pins static const unsigned int intc_irq9_mux[] = { IRQ9_MARK, }; +/* - MMCIF ------------------------------------------------------------------ */ +static const unsigned int mmc_data1_pins[] = { + /* D[0] */ + RCAR_GP_PIN(6, 18), +}; +static const unsigned int mmc_data1_mux[] = { + MMC_D0_MARK, +}; +static const unsigned int mmc_data4_pins[] = { + /* D[0:3] */ + RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), + RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), +}; +static const unsigned int mmc_data4_mux[] = { + MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, +}; +static const unsigned int mmc_data8_pins[] = { + /* D[0:7] */ + RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), + RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), + RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23), + RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), +}; +static const unsigned int mmc_data8_mux[] = { + MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, + MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK, +}; +static const unsigned int mmc_ctrl_pins[] = { + /* CLK, CMD */ + RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17), +}; +static const unsigned int mmc_ctrl_mux[] = { + MMC_CLK_MARK, MMC_CMD_MARK, +}; /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -2683,6 +2717,10 @@ static const struct sh_pfc_pin_group pin SH_PFC_PIN_GROUP(intc_irq7), SH_PFC_PIN_GROUP(intc_irq8), SH_PFC_PIN_GROUP(intc_irq9), + SH_PFC_PIN_GROUP(mmc_data1), + SH_PFC_PIN_GROUP(mmc_data4), + SH_PFC_PIN_GROUP(mmc_data8), + SH_PFC_PIN_GROUP(mmc_ctrl), SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -2869,6 +2907,13 @@ static const char * const intc_groups[] "intc_irq9", }; +static const char * const mmc_groups[] = { + "mmc_data1", + "mmc_data4", + "mmc_data8", + "mmc_ctrl", +}; + static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -3035,6 +3080,7 @@ static const struct sh_pfc_function pinm SH_PFC_FUNCTION(i2c3), SH_PFC_FUNCTION(i2c4), SH_PFC_FUNCTION(intc), + SH_PFC_FUNCTION(mmc), SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2),