diff mbox

[U-Boot,2/8] ARM: highbank: add reset support for Calxeda Midway machine

Message ID 1433462329-10680-3-git-send-email-osp@andrep.de
State Accepted
Delegated to: Tom Rini
Headers show

Commit Message

Andre Przywara June 4, 2015, 11:58 p.m. UTC 
From: Mark Langsdorf <mark.langsdorf@gmail.com>

The Calxeda Midway part has A15 cores, which do not have the Highbank
A9's SCU used there for resetting the chip.
Add code to distinguish between the A9 and the A15 and invoke the
appropriate register writes to support the newer part.

Andre: rework detection of Highbank vs. Midway
Rob: fix Andre's reworked detection

Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com>
Signed-off-by: Andre Przywara <osp@andrep.de>
Signed-off-by: Rob Herring <robh@kernel.org>
---
 board/highbank/highbank.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

Comments

Tom Rini June 13, 2015, 2:09 a.m. UTC | #1 
On Fri, Jun 05, 2015 at 12:58:43AM +0100, Andre Przywara wrote:

> From: Mark Langsdorf <mark.langsdorf@gmail.com>
> 
> The Calxeda Midway part has A15 cores, which do not have the Highbank
> A9's SCU used there for resetting the chip.
> Add code to distinguish between the A9 and the A15 and invoke the
> appropriate register writes to support the newer part.
> 
> Andre: rework detection of Highbank vs. Midway
> Rob: fix Andre's reworked detection
> 
> Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com>
> Signed-off-by: Andre Przywara <osp@andrep.de>
> Signed-off-by: Rob Herring <robh@kernel.org>

Applied to u-boot/master, thanks!
diff mbox

Patch

diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c
index ba254b6..e8132b8 100644
--- a/board/highbank/highbank.c
+++ b/board/highbank/highbank.c
@@ -18,6 +18,7 @@ 
 #define HB_SREG_A9_PWR_REQ		0xfff3cf00
 #define HB_SREG_A9_BOOT_SRC_STAT	0xfff3cf04
 #define HB_SREG_A9_PWRDOM_STAT		0xfff3cf20
+#define HB_SREG_A15_PWR_CTRL		0xfff3c200
 
 #define HB_PWR_SUSPEND			0
 #define HB_PWR_SOFT_RESET		1
@@ -116,10 +117,22 @@  int ft_board_setup(void *fdt, bd_t *bd)
 }
 #endif
 
+static int is_highbank(void)
+{
+	uint32_t midr;
+
+	asm volatile ("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr));
+
+	return (midr & 0xfff0) == 0xc090;
+}
+
 void reset_cpu(ulong addr)
 {
 	writel(HB_PWR_HARD_RESET, HB_SREG_A9_PWR_REQ);
-	writeb(HB_SCU_A9_PWR_OFF, HB_SCU_A9_PWR_STATUS);
+	if (is_highbank())
+		writeb(HB_SCU_A9_PWR_OFF, HB_SCU_A9_PWR_STATUS);
+	else
+		writel(0x1, HB_SREG_A15_PWR_CTRL);
 
 	wfi();
 }