From patchwork Thu Jun 4 23:30:40 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 480924 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4156C140281 for ; Fri, 5 Jun 2015 09:30:45 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753518AbbFDXao (ORCPT ); Thu, 4 Jun 2015 19:30:44 -0400 Received: from mail-lb0-f169.google.com ([209.85.217.169]:36164 "EHLO mail-lb0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752335AbbFDXan (ORCPT ); Thu, 4 Jun 2015 19:30:43 -0400 Received: by lbbqq2 with SMTP id qq2so36211064lbb.3 for ; Thu, 04 Jun 2015 16:30:42 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id:organization :user-agent:in-reply-to:references:mime-version :content-transfer-encoding:content-type; bh=JtavQ08IHXHrljq9hO4zVgoOO5PrCfORJwKM4XZrZBg=; b=XbpRj5k8eV55yGpLAYPptx7/byyLFNRW43OfoPPTXtae6mS7DkYAqaXU8t0ffTKYML 9Jvr9kz2jwW9A/PaTGjg4cQVlg0yBJIPZxIGj8y7z5EhLFkiVI3Xsj/zdtcULFYt+A6K ZcIVUuIrBw6TEVd+qDjqEJpdqIIAu7xXROizIQ9G8Gq5y0P+Bfyu0h4GJHZjXaNyRqK7 U3TY7qxcGO1+QIzOJRUBs286gcXMD4RIUExGKoaHFhC7GuyVyLCcUg43nDxHuQtrx1BF Z3TyFjfbQsqRr9jFPao5fO9kWaCVuKyPuKwmo7GS8y0eeWiEs4OGuMu1zCg3/dh/vQY8 GAyg== X-Gm-Message-State: ALoCoQmPTEL//uoLCy7fC+l7cyJG4M6/waRjQU9ZlFKiUgytJpttNjLutVXwX4MB99SiqadjwlYv X-Received: by 10.112.188.194 with SMTP id gc2mr462882lbc.25.1433460642328; Thu, 04 Jun 2015 16:30:42 -0700 (PDT) Received: from wasted.cogentembedded.com (ppp85-141-196-196.pppoe.mtu-net.ru. [85.141.196.196]) by mx.google.com with ESMTPSA id s8sm1183115las.29.2015.06.04.16.30.40 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 04 Jun 2015 16:30:41 -0700 (PDT) From: Sergei Shtylyov To: linus.walleij@linaro.org, linux-sh@vger.kernel.org, laurent.pinchart@ideasonboard.com, linux-gpio@vger.kernel.org Subject: [PATCH v2 3/4] sh-pfc: r8a7790: remove non-existing GPIO pins Date: Fri, 05 Jun 2015 02:30:40 +0300 Message-ID: <20198588.C6cLT92jQ4@wasted.cogentembedded.com> Organization: Cogent Embedded Inc. User-Agent: KMail/4.14.7 (Linux/3.19.8-100.fc20.x86_64; KDE/4.14.7; x86_64; ; ) In-Reply-To: <4326653.qPvIJDU6F2@wasted.cogentembedded.com> References: <4326653.qPvIJDU6F2@wasted.cogentembedded.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Laurent Pinchart GPIO banks 1 and 2 are missing pins 30 and 31. Remove them. Signed-off-by: Laurent Pinchart Signed-off-by: Sergei Shtylyov --- Changes in version 2: - renamed the patch. drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Index: linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7790.c =================================================================== --- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -27,10 +27,27 @@ #include "core.h" #include "sh_pfc.h" +#define PORT_GP_30(bank, fn, sfx) \ + PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ + PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ + PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ + PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ + PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ + PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ + PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ + PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ + PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ + PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ + PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ + PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ + PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \ + PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \ + PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx) + #define CPU_ALL_PORT(fn, sfx) \ PORT_GP_32(0, fn, sfx), \ - PORT_GP_32(1, fn, sfx), \ - PORT_GP_32(2, fn, sfx), \ + PORT_GP_30(1, fn, sfx), \ + PORT_GP_30(2, fn, sfx), \ PORT_GP_32(3, fn, sfx), \ PORT_GP_32(4, fn, sfx), \ PORT_GP_32(5, fn, sfx)