diff mbox

ARM: tegra: Enable CPUFreq support for Tegra124 Chromebooks

Message ID 1433331821-9648-1-git-send-email-jonathanh@nvidia.com
State Accepted, archived
Headers show

Commit Message

Jon Hunter June 3, 2015, 11:43 a.m. UTC
Add the device-tree DFLL clock node and CPU regulator phandle for
tegra124 chromebooks to enable CPUFreq support on these boards.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>

---
This has been tested on a tegra124 nyan-big by using the userspace
CPUFreq governor with a simple CPU benchmark to measure the time taken
for the test to execute.

The tegra124 chromebooks use the same ams,as3722 PMIC as the Jetson TK1
board and hence, this change is based upon that for the Jetson TK1.

 arch/arm/boot/dts/tegra124-nyan.dtsi | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

Comments

Jon Hunter June 3, 2015, 11:44 a.m. UTC | #1
Adding LAKML. Jon

On 03/06/15 12:43, Jon Hunter wrote:
> Add the device-tree DFLL clock node and CPU regulator phandle for
> tegra124 chromebooks to enable CPUFreq support on these boards.
> 
> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
> 
> ---
> This has been tested on a tegra124 nyan-big by using the userspace
> CPUFreq governor with a simple CPU benchmark to measure the time taken
> for the test to execute.
> 
> The tegra124 chromebooks use the same ams,as3722 PMIC as the Jetson TK1
> board and hence, this change is based upon that for the Jetson TK1.
> 
>  arch/arm/boot/dts/tegra124-nyan.dtsi | 15 ++++++++++++++-
>  1 file changed, 14 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi
> index a9aec23e06f2..40c23a0b7cfc 100644
> --- a/arch/arm/boot/dts/tegra124-nyan.dtsi
> +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi
> @@ -159,7 +159,7 @@
>  				vin-ldo9-10-supply = <&vdd_5v0_sys>;
>  				vin-ldo11-supply = <&vdd_3v3_run>;
>  
> -				sd0 {
> +				vdd_cpu: sd0 {
>  					regulator-name = "+VDD_CPU_AP";
>  					regulator-min-microvolt = <700000>;
>  					regulator-max-microvolt = <1350000>;
> @@ -397,6 +397,13 @@
>  		non-removable;
>  	};
>  
> +	/* CPU DFLL clock */
> +	clock@0,70110000 {
> +		status = "okay";
> +		vdd-cpu-supply = <&vdd_cpu>;
> +		nvidia,i2c-fs-rate = <400000>;
> +	};
> +
>  	ahub@0,70300000 {
>  		i2s@0,70301100 {
>  			status = "okay";
> @@ -487,6 +494,12 @@
>  		};
>  	};
>  
> +	cpus {
> +		cpu@0 {
> +			vdd-cpu-supply = <&vdd_cpu>;
> +		};
> +	};
> +
>  	gpio-keys {
>  		compatible = "gpio-keys";
>  
> 
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Jon Hunter July 13, 2015, 1:08 p.m. UTC | #2
On 03/06/15 12:44, Jon Hunter wrote:
> Adding LAKML. Jon
> 
> On 03/06/15 12:43, Jon Hunter wrote:
>> Add the device-tree DFLL clock node and CPU regulator phandle for
>> tegra124 chromebooks to enable CPUFreq support on these boards.
>>
>> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
>>
>> ---
>> This has been tested on a tegra124 nyan-big by using the userspace
>> CPUFreq governor with a simple CPU benchmark to measure the time taken
>> for the test to execute.
>>
>> The tegra124 chromebooks use the same ams,as3722 PMIC as the Jetson TK1
>> board and hence, this change is based upon that for the Jetson TK1.
>>
>>  arch/arm/boot/dts/tegra124-nyan.dtsi | 15 ++++++++++++++-
>>  1 file changed, 14 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi
>> index a9aec23e06f2..40c23a0b7cfc 100644
>> --- a/arch/arm/boot/dts/tegra124-nyan.dtsi
>> +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi
>> @@ -159,7 +159,7 @@
>>  				vin-ldo9-10-supply = <&vdd_5v0_sys>;
>>  				vin-ldo11-supply = <&vdd_3v3_run>;
>>  
>> -				sd0 {
>> +				vdd_cpu: sd0 {
>>  					regulator-name = "+VDD_CPU_AP";
>>  					regulator-min-microvolt = <700000>;
>>  					regulator-max-microvolt = <1350000>;
>> @@ -397,6 +397,13 @@
>>  		non-removable;
>>  	};
>>  
>> +	/* CPU DFLL clock */
>> +	clock@0,70110000 {
>> +		status = "okay";
>> +		vdd-cpu-supply = <&vdd_cpu>;
>> +		nvidia,i2c-fs-rate = <400000>;
>> +	};
>> +
>>  	ahub@0,70300000 {
>>  		i2s@0,70301100 {
>>  			status = "okay";
>> @@ -487,6 +494,12 @@
>>  		};
>>  	};
>>  
>> +	cpus {
>> +		cpu@0 {
>> +			vdd-cpu-supply = <&vdd_cpu>;
>> +		};
>> +	};
>> +
>>  	gpio-keys {
>>  		compatible = "gpio-keys";

Stephen, Thierry,

Are you ok with this change?

Jon
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Tomeu Vizoso Sept. 3, 2015, 1:40 p.m. UTC | #3
On 13 July 2015 at 15:08, Jon Hunter <jonathanh@nvidia.com> wrote:
> On 03/06/15 12:44, Jon Hunter wrote:
>> Adding LAKML. Jon
>>
>> On 03/06/15 12:43, Jon Hunter wrote:
>>> Add the device-tree DFLL clock node and CPU regulator phandle for
>>> tegra124 chromebooks to enable CPUFreq support on these boards.

Ping.

Thanks,

Tomeu

>>> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
>>>
>>> ---
>>> This has been tested on a tegra124 nyan-big by using the userspace
>>> CPUFreq governor with a simple CPU benchmark to measure the time taken
>>> for the test to execute.
>>>
>>> The tegra124 chromebooks use the same ams,as3722 PMIC as the Jetson TK1
>>> board and hence, this change is based upon that for the Jetson TK1.
>>>
>>>  arch/arm/boot/dts/tegra124-nyan.dtsi | 15 ++++++++++++++-
>>>  1 file changed, 14 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi
>>> index a9aec23e06f2..40c23a0b7cfc 100644
>>> --- a/arch/arm/boot/dts/tegra124-nyan.dtsi
>>> +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi
>>> @@ -159,7 +159,7 @@
>>>                              vin-ldo9-10-supply = <&vdd_5v0_sys>;
>>>                              vin-ldo11-supply = <&vdd_3v3_run>;
>>>
>>> -                            sd0 {
>>> +                            vdd_cpu: sd0 {
>>>                                      regulator-name = "+VDD_CPU_AP";
>>>                                      regulator-min-microvolt = <700000>;
>>>                                      regulator-max-microvolt = <1350000>;
>>> @@ -397,6 +397,13 @@
>>>              non-removable;
>>>      };
>>>
>>> +    /* CPU DFLL clock */
>>> +    clock@0,70110000 {
>>> +            status = "okay";
>>> +            vdd-cpu-supply = <&vdd_cpu>;
>>> +            nvidia,i2c-fs-rate = <400000>;
>>> +    };
>>> +
>>>      ahub@0,70300000 {
>>>              i2s@0,70301100 {
>>>                      status = "okay";
>>> @@ -487,6 +494,12 @@
>>>              };
>>>      };
>>>
>>> +    cpus {
>>> +            cpu@0 {
>>> +                    vdd-cpu-supply = <&vdd_cpu>;
>>> +            };
>>> +    };
>>> +
>>>      gpio-keys {
>>>              compatible = "gpio-keys";
>
> Stephen, Thierry,
>
> Are you ok with this change?
>
> Jon
> --
> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
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Thierry Reding Sept. 15, 2015, 8:12 a.m. UTC | #4
On Thu, Sep 03, 2015 at 03:40:45PM +0200, Tomeu Vizoso wrote:
> On 13 July 2015 at 15:08, Jon Hunter <jonathanh@nvidia.com> wrote:
> > On 03/06/15 12:44, Jon Hunter wrote:
> >> Adding LAKML. Jon
> >>
> >> On 03/06/15 12:43, Jon Hunter wrote:
> >>> Add the device-tree DFLL clock node and CPU regulator phandle for
> >>> tegra124 chromebooks to enable CPUFreq support on these boards.
> 
> Ping.
> 
> Thanks,

Sorry that this has gone unnoticed for so long. I've applied it now to
the for-4.4/dt branch.

Tomeu, do you want me to add your Tested-by, Reviewed-by or Acked-by
before I push this out?

Thierry
Tomeu Vizoso Sept. 15, 2015, 9 a.m. UTC | #5
On 15 September 2015 at 10:12, Thierry Reding <thierry.reding@gmail.com> wrote:
> On Thu, Sep 03, 2015 at 03:40:45PM +0200, Tomeu Vizoso wrote:
>> On 13 July 2015 at 15:08, Jon Hunter <jonathanh@nvidia.com> wrote:
>> > On 03/06/15 12:44, Jon Hunter wrote:
>> >> Adding LAKML. Jon
>> >>
>> >> On 03/06/15 12:43, Jon Hunter wrote:
>> >>> Add the device-tree DFLL clock node and CPU regulator phandle for
>> >>> tegra124 chromebooks to enable CPUFreq support on these boards.
>>
>> Ping.
>>
>> Thanks,
>
> Sorry that this has gone unnoticed for so long. I've applied it now to
> the for-4.4/dt branch.
>
> Tomeu, do you want me to add your Tested-by, Reviewed-by or Acked-by
> before I push this out?

I haven't done proper tests, but I have tested for several weeks a
branch containing these changes on a nyan-big and have found no
issues.

You can add my Reviewed-by though. Sorry for not having made this clear.

Thanks,

Tomeu

> Thierry
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Jon Hunter Nov. 4, 2015, 12:16 p.m. UTC | #6
On 15/09/15 10:00, Tomeu Vizoso wrote:
> On 15 September 2015 at 10:12, Thierry Reding <thierry.reding@gmail.com> wrote:
>> On Thu, Sep 03, 2015 at 03:40:45PM +0200, Tomeu Vizoso wrote:
>>> On 13 July 2015 at 15:08, Jon Hunter <jonathanh@nvidia.com> wrote:
>>>> On 03/06/15 12:44, Jon Hunter wrote:
>>>>> Adding LAKML. Jon
>>>>>
>>>>> On 03/06/15 12:43, Jon Hunter wrote:
>>>>>> Add the device-tree DFLL clock node and CPU regulator phandle for
>>>>>> tegra124 chromebooks to enable CPUFreq support on these boards.
>>>
>>> Ping.
>>>
>>> Thanks,
>>
>> Sorry that this has gone unnoticed for so long. I've applied it now to
>> the for-4.4/dt branch.
>>
>> Tomeu, do you want me to add your Tested-by, Reviewed-by or Acked-by
>> before I push this out?
> 
> I haven't done proper tests, but I have tested for several weeks a
> branch containing these changes on a nyan-big and have found no
> issues.
> 
> You can add my Reviewed-by though. Sorry for not having made this clear.

I have noticed that system suspend to LP1 is not working on the nyan-big
with linux-next and never exits suspend. It appears that this patch is
the culprit. I tested cpufreq was changing the frequency as expected but
I did not test suspend.

I have tested suspend on the jetson-tk1 with linux-next that also has
cpufreq enabled and do not see any problems.

Adding Mikko ... Mikko do you know of any reason why cpufreq could cause
problems with suspend? I am guessing it is to do with the different
clock used for the CPUs. Any thoughts?

Tomeu, have you tried suspend on a nyan-big with next?

I am testing with "rtcwake -d rtc1 -m mem -s 5".

Thierry, we may need to comment out these changes for 4.3 or revert this
patch altogether.

Cheers
Jon
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Jon Hunter Nov. 4, 2015, 12:19 p.m. UTC | #7
Correcting Mikko's email ...

On 04/11/15 12:16, Jon Hunter wrote:
> 
> On 15/09/15 10:00, Tomeu Vizoso wrote:
>> On 15 September 2015 at 10:12, Thierry Reding <thierry.reding@gmail.com> wrote:
>>> On Thu, Sep 03, 2015 at 03:40:45PM +0200, Tomeu Vizoso wrote:
>>>> On 13 July 2015 at 15:08, Jon Hunter <jonathanh@nvidia.com> wrote:
>>>>> On 03/06/15 12:44, Jon Hunter wrote:
>>>>>> Adding LAKML. Jon
>>>>>>
>>>>>> On 03/06/15 12:43, Jon Hunter wrote:
>>>>>>> Add the device-tree DFLL clock node and CPU regulator phandle for
>>>>>>> tegra124 chromebooks to enable CPUFreq support on these boards.
>>>>
>>>> Ping.
>>>>
>>>> Thanks,
>>>
>>> Sorry that this has gone unnoticed for so long. I've applied it now to
>>> the for-4.4/dt branch.
>>>
>>> Tomeu, do you want me to add your Tested-by, Reviewed-by or Acked-by
>>> before I push this out?
>>
>> I haven't done proper tests, but I have tested for several weeks a
>> branch containing these changes on a nyan-big and have found no
>> issues.
>>
>> You can add my Reviewed-by though. Sorry for not having made this clear.
> 
> I have noticed that system suspend to LP1 is not working on the nyan-big
> with linux-next and never exits suspend. It appears that this patch is
> the culprit. I tested cpufreq was changing the frequency as expected but
> I did not test suspend.
> 
> I have tested suspend on the jetson-tk1 with linux-next that also has
> cpufreq enabled and do not see any problems.
> 
> Adding Mikko ... Mikko do you know of any reason why cpufreq could cause
> problems with suspend? I am guessing it is to do with the different
> clock used for the CPUs. Any thoughts?
> 
> Tomeu, have you tried suspend on a nyan-big with next?
> 
> I am testing with "rtcwake -d rtc1 -m mem -s 5".
> 
> Thierry, we may need to comment out these changes for 4.3 or revert this
> patch altogether.
> 
> Cheers
> Jon
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> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
> the body of a message to majordomo@vger.kernel.org
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Jon Hunter Nov. 4, 2015, 1:23 p.m. UTC | #8
On 04/11/15 12:19, Jon Hunter wrote:
> Correcting Mikko's email ...
> 
> On 04/11/15 12:16, Jon Hunter wrote:
>>
>> On 15/09/15 10:00, Tomeu Vizoso wrote:
>>> On 15 September 2015 at 10:12, Thierry Reding <thierry.reding@gmail.com> wrote:
>>>> On Thu, Sep 03, 2015 at 03:40:45PM +0200, Tomeu Vizoso wrote:
>>>>> On 13 July 2015 at 15:08, Jon Hunter <jonathanh@nvidia.com> wrote:
>>>>>> On 03/06/15 12:44, Jon Hunter wrote:
>>>>>>> Adding LAKML. Jon
>>>>>>>
>>>>>>> On 03/06/15 12:43, Jon Hunter wrote:
>>>>>>>> Add the device-tree DFLL clock node and CPU regulator phandle for
>>>>>>>> tegra124 chromebooks to enable CPUFreq support on these boards.
>>>>>
>>>>> Ping.
>>>>>
>>>>> Thanks,
>>>>
>>>> Sorry that this has gone unnoticed for so long. I've applied it now to
>>>> the for-4.4/dt branch.
>>>>
>>>> Tomeu, do you want me to add your Tested-by, Reviewed-by or Acked-by
>>>> before I push this out?
>>>
>>> I haven't done proper tests, but I have tested for several weeks a
>>> branch containing these changes on a nyan-big and have found no
>>> issues.
>>>
>>> You can add my Reviewed-by though. Sorry for not having made this clear.
>>
>> I have noticed that system suspend to LP1 is not working on the nyan-big
>> with linux-next and never exits suspend. It appears that this patch is
>> the culprit. I tested cpufreq was changing the frequency as expected but
>> I did not test suspend.

By the way, LP2 works fine with this change, it is just when LP1 is
enabled (which is the default).

Jon
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diff mbox

Patch

diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi
index a9aec23e06f2..40c23a0b7cfc 100644
--- a/arch/arm/boot/dts/tegra124-nyan.dtsi
+++ b/arch/arm/boot/dts/tegra124-nyan.dtsi
@@ -159,7 +159,7 @@ 
 				vin-ldo9-10-supply = <&vdd_5v0_sys>;
 				vin-ldo11-supply = <&vdd_3v3_run>;
 
-				sd0 {
+				vdd_cpu: sd0 {
 					regulator-name = "+VDD_CPU_AP";
 					regulator-min-microvolt = <700000>;
 					regulator-max-microvolt = <1350000>;
@@ -397,6 +397,13 @@ 
 		non-removable;
 	};
 
+	/* CPU DFLL clock */
+	clock@0,70110000 {
+		status = "okay";
+		vdd-cpu-supply = <&vdd_cpu>;
+		nvidia,i2c-fs-rate = <400000>;
+	};
+
 	ahub@0,70300000 {
 		i2s@0,70301100 {
 			status = "okay";
@@ -487,6 +494,12 @@ 
 		};
 	};
 
+	cpus {
+		cpu@0 {
+			vdd-cpu-supply = <&vdd_cpu>;
+		};
+	};
+
 	gpio-keys {
 		compatible = "gpio-keys";