From patchwork Tue Mar 16 21:44:44 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 47977 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 96A30B7CD5 for ; Thu, 18 Mar 2010 11:51:54 +1100 (EST) Received: from localhost ([127.0.0.1]:45968 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Ns3uG-00006G-SL for incoming@patchwork.ozlabs.org; Wed, 17 Mar 2010 20:48:12 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Ns3sy-0008VC-0o for qemu-devel@nongnu.org; Wed, 17 Mar 2010 20:46:52 -0400 Received: from [199.232.76.173] (port=52443 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Ns3sx-0008UF-28 for qemu-devel@nongnu.org; Wed, 17 Mar 2010 20:46:51 -0400 Received: from Debian-exim by monty-python.gnu.org with spam-scanned (Exim 4.60) (envelope-from ) id 1Ns3sw-0000Hi-2u for qemu-devel@nongnu.org; Wed, 17 Mar 2010 20:46:50 -0400 Received: from are.twiddle.net ([75.149.56.221]:38371) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Ns3st-0000HF-QW for qemu-devel@nongnu.org; Wed, 17 Mar 2010 20:46:48 -0400 Received: by are.twiddle.net (Postfix, from userid 5000) id 5D24AB0D; Wed, 17 Mar 2010 17:46:45 -0700 (PDT) Message-Id: <75d6903dabf194856dc87356e99f39dfe663d239.1268868813.git.rth@twiddle.net> In-Reply-To: References: From: Richard Henderson Date: Tue, 16 Mar 2010 14:44:44 -0700 To: qemu-devel@nongnu.org X-detected-operating-system: by monty-python.gnu.org: GNU/Linux 2.6 (newer, 2) Subject: [Qemu-devel] [PATCH 7/8] target-alpha: Use non-inverted arguments to gen_{f}cmov. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The inverted conditions as argument to the function looks wrong at a glance inside translate_one. Since we have an easy function to produce the inversion now, use it. Signed-off-by: Richard Henderson --- target-alpha/translate.c | 37 +++++++++++++++++++------------------ 1 files changed, 19 insertions(+), 18 deletions(-) diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 3fa32b3..b845094 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -394,9 +394,10 @@ static void gen_fbcond(DisasContext *ctx, TCGCond cond, int ra, int32_t disp) gen_bcond_pcload(ctx, disp, lab_true); } -static inline void gen_cmov(TCGCond inv_cond, int ra, int rb, int rc, - int islit, uint8_t lit, int mask) +static void gen_cmov(TCGCond cond, int ra, int rb, int rc, + int islit, uint8_t lit, int mask) { + TCGCond inv_cond = tcg_invert_cond(cond); int l1; if (unlikely(rc == 31)) @@ -426,7 +427,7 @@ static inline void gen_cmov(TCGCond inv_cond, int ra, int rb, int rc, gen_set_label(l1); } -static void gen_fcmov(TCGCond inv_cond, int ra, int rb, int rc) +static void gen_fcmov(TCGCond cond, int ra, int rb, int rc) { TCGv va = cpu_fir[ra]; int l1; @@ -439,7 +440,7 @@ static void gen_fcmov(TCGCond inv_cond, int ra, int rb, int rc) } l1 = gen_new_label(); - gen_fbcond_internal(inv_cond, va, l1); + gen_fbcond_internal(tcg_invert_cond(cond), va, l1); if (rb != 31) tcg_gen_mov_i64(cpu_fir[rc], cpu_fir[rb]); @@ -1765,11 +1766,11 @@ static inline int translate_one(DisasContext *ctx, uint32_t insn) break; case 0x14: /* CMOVLBS */ - gen_cmov(TCG_COND_EQ, ra, rb, rc, islit, lit, 1); + gen_cmov(TCG_COND_NE, ra, rb, rc, islit, lit, 1); break; case 0x16: /* CMOVLBC */ - gen_cmov(TCG_COND_NE, ra, rb, rc, islit, lit, 1); + gen_cmov(TCG_COND_EQ, ra, rb, rc, islit, lit, 1); break; case 0x20: /* BIS */ @@ -1789,11 +1790,11 @@ static inline int translate_one(DisasContext *ctx, uint32_t insn) break; case 0x24: /* CMOVEQ */ - gen_cmov(TCG_COND_NE, ra, rb, rc, islit, lit, 0); + gen_cmov(TCG_COND_EQ, ra, rb, rc, islit, lit, 0); break; case 0x26: /* CMOVNE */ - gen_cmov(TCG_COND_EQ, ra, rb, rc, islit, lit, 0); + gen_cmov(TCG_COND_NE, ra, rb, rc, islit, lit, 0); break; case 0x28: /* ORNOT */ @@ -1829,11 +1830,11 @@ static inline int translate_one(DisasContext *ctx, uint32_t insn) break; case 0x44: /* CMOVLT */ - gen_cmov(TCG_COND_GE, ra, rb, rc, islit, lit, 0); + gen_cmov(TCG_COND_LT, ra, rb, rc, islit, lit, 0); break; case 0x46: /* CMOVGE */ - gen_cmov(TCG_COND_LT, ra, rb, rc, islit, lit, 0); + gen_cmov(TCG_COND_GE, ra, rb, rc, islit, lit, 0); break; case 0x48: /* EQV */ @@ -1873,11 +1874,11 @@ static inline int translate_one(DisasContext *ctx, uint32_t insn) break; case 0x64: /* CMOVLE */ - gen_cmov(TCG_COND_GT, ra, rb, rc, islit, lit, 0); + gen_cmov(TCG_COND_LE, ra, rb, rc, islit, lit, 0); break; case 0x66: /* CMOVGT */ - gen_cmov(TCG_COND_LE, ra, rb, rc, islit, lit, 0); + gen_cmov(TCG_COND_GT, ra, rb, rc, islit, lit, 0); break; case 0x6C: /* IMPLVER */ @@ -2351,27 +2352,27 @@ static inline int translate_one(DisasContext *ctx, uint32_t insn) break; case 0x02A: /* FCMOVEQ */ - gen_fcmov(TCG_COND_NE, ra, rb, rc); + gen_fcmov(TCG_COND_EQ, ra, rb, rc); break; case 0x02B: /* FCMOVNE */ - gen_fcmov(TCG_COND_EQ, ra, rb, rc); + gen_fcmov(TCG_COND_NE, ra, rb, rc); break; case 0x02C: /* FCMOVLT */ - gen_fcmov(TCG_COND_GE, ra, rb, rc); + gen_fcmov(TCG_COND_LT, ra, rb, rc); break; case 0x02D: /* FCMOVGE */ - gen_fcmov(TCG_COND_LT, ra, rb, rc); + gen_fcmov(TCG_COND_GE, ra, rb, rc); break; case 0x02E: /* FCMOVLE */ - gen_fcmov(TCG_COND_GT, ra, rb, rc); + gen_fcmov(TCG_COND_LE, ra, rb, rc); break; case 0x02F: /* FCMOVGT */ - gen_fcmov(TCG_COND_LE, ra, rb, rc); + gen_fcmov(TCG_COND_GT, ra, rb, rc); break; case 0x030: /* CVTQL */