From patchwork Wed Mar 17 17:04:45 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 47961 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id EF877B7D2A for ; Thu, 18 Mar 2010 05:18:40 +1100 (EST) Received: from localhost ([127.0.0.1]:56056 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NrxpG-0002Ne-2v for incoming@patchwork.ozlabs.org; Wed, 17 Mar 2010 14:18:38 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Nrwfs-0004nv-7W for qemu-devel@nongnu.org; Wed, 17 Mar 2010 13:04:52 -0400 Received: from [199.232.76.173] (port=42372 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Nrwfr-0004nR-IP for qemu-devel@nongnu.org; Wed, 17 Mar 2010 13:04:51 -0400 Received: from Debian-exim by monty-python.gnu.org with spam-scanned (Exim 4.60) (envelope-from ) id 1Nrwfq-00051W-FD for qemu-devel@nongnu.org; Wed, 17 Mar 2010 13:04:51 -0400 Received: from are.twiddle.net ([75.149.56.221]:42656) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Nrwfp-00051O-Tf for qemu-devel@nongnu.org; Wed, 17 Mar 2010 13:04:50 -0400 Received: from anchor.twiddle.home (anchor.twiddle.home [172.31.0.4]) by are.twiddle.net (Postfix) with ESMTPSA id 26CD9525; Wed, 17 Mar 2010 10:04:46 -0700 (PDT) Message-ID: <4BA10BAD.8010605@twiddle.net> Date: Wed, 17 Mar 2010 10:04:45 -0700 From: Richard Henderson User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.8) Gecko/20100301 Fedora/3.0.3-1.fc12 Thunderbird/3.0.3 MIME-Version: 1.0 To: Stuart Brady Subject: Re: [Qemu-devel] [PATCH 3/4] tcg-hppa: Finish the port. References: <6880f84577b97d0334b95f6ce031e61c65c2e88b.1268754659.git.rth@twiddle.net> <20100317015829.GC23195@zubnet.me.uk> <4BA0ED8C.8000404@twiddle.net> In-Reply-To: <4BA0ED8C.8000404@twiddle.net> X-detected-operating-system: by monty-python.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: qemu-devel@nongnu.org X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org On 03/17/2010 07:56 AM, Richard Henderson wrote: > Since Aurelien's generic div/rem patch I could simply remove all > that millicode stuff, including that tcg_reg_free, and let the > generic code handle this instead. Which would get to the same > millicode routine via one or two extra levels of indirection. The following patch implements this, and does indeed work. r~ ---- diff --git a/tcg/hppa/tcg-target.c b/tcg/hppa/tcg-target.c index fe96779..c6ba593 100644 --- a/tcg/hppa/tcg-target.c +++ b/tcg/hppa/tcg-target.c @@ -193,11 +193,6 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) ct->ct |= TCG_CT_REG; tcg_regset_set32(ct->u.regs, 0, 0xffffffff); break; - case 'c': - /* millicode division return register. */ - ct->ct | TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, 1u << TCG_REG_RET1); - break; case 'L': /* qemu_ld/st constraint */ ct->ct |= TCG_CT_REG; tcg_regset_set32(ct->u.regs, 0, 0xffffffff); @@ -680,65 +675,6 @@ static void tcg_out_xmpyu(TCGContext *s, int retl, int reth, } } -/* We define the following table directly in assembly so that we - can avoid getting PLABEL addresses. */ - -extern tcg_target_long qemu_milli[4]; -asm(".section .rodata\n\ - .import $$divI,millicode\n\ - .import $$remI,millicode\n\ - .import $$divU,millicode\n\ - .import $$remU,millicode\n\ - .type qemu_milli,@object\n\ - .size qemu_milli,16\n\ -qemu_milli:\n\ - .word $$divI\n\ - .word $$remI\n\ - .word $$divU\n\ - .word $$remU\n\ - .previous"); - -#define MILLI_DIVI 0 -#define MILLI_REMI 1 -#define MILLI_DIVU 2 -#define MILLI_REMU 3 - -/* ??? Move this up in tcg.c. */ -static void tcg_reg_free(TCGContext *, int); - -/* Note that the return is constrained to be r29, and the inputs are - constrained to not be in the first two parameter registers. Otherwise, - we clobber r1 and r31, which are already marked as reserved. */ -static void tcg_out_milli(TCGContext *s, int arg1, int arg2, int which) -{ - tcg_target_long routine, disp; - - /* The parameter registers are clobbered. Store them back to their - stack slots before we lose the contents. */ - tcg_reg_free(s, TCG_REG_R26); - tcg_reg_free(s, TCG_REG_R25); - tcg_out_mov(s, TCG_REG_R26, arg1); - - routine = qemu_milli[which]; - disp = (routine - ((tcg_target_long)s->code_ptr + 8)) >> 2; - - if (check_fit_tl(disp, 17)) { - tcg_out32(s, INSN_BL | INSN_R2(TCG_REG_R31) | reassemble_17(disp)); - } else { - uint32_t hi, lo; - - hi = routine >> 11; - lo = routine & 0x7ff; - - tcg_out32(s, INSN_LDIL | INSN_R2(TCG_REG_R1) | reassemble_21(hi)); - tcg_out32(s, INSN_BLE_SR4 | INSN_R2(TCG_REG_R1) - | reassemble_17(lo >> 2)); - } - - /* Second input copy in call delay slot. */ - tcg_out_mov(s, TCG_REG_R25, arg2); -} - static void tcg_out_branch(TCGContext *s, int label_index, int nul) { TCGLabel *l = &s->labels[label_index]; @@ -1443,19 +1379,6 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args, tcg_out_xmpyu(s, args[0], args[1], args[2], args[3]); break; - case INDEX_op_div_i32: - tcg_out_milli(s, args[1], args[2], MILLI_DIVI); - break; - case INDEX_op_divu_i32: - tcg_out_milli(s, args[1], args[2], MILLI_DIVU); - break; - case INDEX_op_rem_i32: - tcg_out_milli(s, args[1], args[2], MILLI_REMI); - break; - case INDEX_op_remu_i32: - tcg_out_milli(s, args[1], args[2], MILLI_REMU); - break; - case INDEX_op_bswap16_i32: tcg_out_bswap16(s, args[0], args[1], 0); break; @@ -1590,11 +1513,6 @@ static const TCGTargetOpDef hppa_op_defs[] = { { INDEX_op_mul_i32, { "r", "r", "r" } }, { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } }, - { INDEX_op_div_i32, { "c", "L", "L" } }, - { INDEX_op_divu_i32, { "c", "L", "L" } }, - { INDEX_op_rem_i32, { "c", "L", "L" } }, - { INDEX_op_remu_i32, { "c", "L", "L" } }, - { INDEX_op_shl_i32, { "r", "r", "ri" } }, { INDEX_op_shr_i32, { "r", "r", "ri" } }, { INDEX_op_sar_i32, { "r", "r", "ri" } }, diff --git a/tcg/hppa/tcg-target.h b/tcg/hppa/tcg-target.h index cd44deb..007aa7a 100644 --- a/tcg/hppa/tcg-target.h +++ b/tcg/hppa/tcg-target.h @@ -82,7 +82,7 @@ enum { #define TCG_TARGET_STACK_GROWSUP /* optional instructions */ -#define TCG_TARGET_HAS_div_i32 +// #define TCG_TARGET_HAS_div_i32 #define TCG_TARGET_HAS_rot_i32 #define TCG_TARGET_HAS_ext8s_i32 #define TCG_TARGET_HAS_ext16s_i32