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[04/13] target-s390x: change CHRL and CGHRL format to RIL-b

Message ID 1433193897-24110-5-git-send-email-aurelien@aurel32.net
State New
Headers show

Commit Message

Aurelien Jarno June 1, 2015, 9:24 p.m. UTC 
Change to match the PoP. In practice both format RIL-a and RIL-b have
the same fields. They differ on the way we decode the fields, and it's
done correctly in QEMU.

Cc: Alexander Graf <agraf@suse.de>
Cc: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 target-s390x/insn-data.def | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Richard Henderson June 2, 2015, 1:38 a.m. UTC | #1 
On 06/01/2015 02:24 PM, Aurelien Jarno wrote:
> Change to match the PoP. In practice both format RIL-a and RIL-b have
> the same fields. They differ on the way we decode the fields, and it's
> done correctly in QEMU.
>
> Cc: Alexander Graf<agraf@suse.de>
> Cc: Richard Henderson<rth@twiddle.net>
> Signed-off-by: Aurelien Jarno<aurelien@aurel32.net>
> ---
>   target-s390x/insn-data.def | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Richard Henderson <rth@twiddle.net>

r~
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Patch

diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def
index f83445a..7649098 100644
--- a/target-s390x/insn-data.def
+++ b/target-s390x/insn-data.def
@@ -159,8 +159,8 @@ 
     C(0xe55c, CHSI,    SIL,   GIE, m1_32s, i2, 0, 0, 0, cmps64)
     C(0xe558, CGHSI,   SIL,   GIE, m1_64, i2, 0, 0, 0, cmps64)
 /* COMPARE HALFWORD RELATIVE LONG */
-    C(0xc605, CHRL,    RIL_a, GIE, r1_o, mri2_32s, 0, 0, 0, cmps32)
-    C(0xc604, CGHRL,   RIL_a, GIE, r1_o, mri2_64, 0, 0, 0, cmps64)
+    C(0xc605, CHRL,    RIL_b, GIE, r1_o, mri2_32s, 0, 0, 0, cmps32)
+    C(0xc604, CGHRL,   RIL_b, GIE, r1_o, mri2_64, 0, 0, 0, cmps64)
 
 /* COMPARE LOGICAL */
     C(0x1500, CLR,     RR_a,  Z,   r1, r2, 0, 0, 0, cmpu32)