| Message ID | 1433183008-13086-1-git-send-email-hdegoede@redhat.com |
|---|---|
| State | Accepted, archived |
| Commit | ec80749dfd859b560e8864d665d38d7a63e6a7f2 |
| Headers | show |
Hi Hans, On Tue, Jun 2, 2015 at 4:23 AM, Hans de Goede <hdegoede@redhat.com> wrote: > The usb-clk on sun8i a23 and a33 SoCs is similar to the ones found > on sun6i-a31 SoCs but instead of a 3th phy the a23 / a33 have a hsic > interface which gets enabled by almost the same bits as used on > the a31 for the 3th phy, but not exactly the same bits so we need > a new compatible for this. Minor spelling note: it's "3rd" not "3th". Thanks,
On Tue, Jun 2, 2015 at 2:23 AM, Hans de Goede <hdegoede@redhat.com> wrote: > The usb-clk on sun8i a23 and a33 SoCs is similar to the ones found > on sun6i-a31 SoCs but instead of a 3th phy the a23 / a33 have a hsic > interface which gets enabled by almost the same bits as used on > the a31 for the 3th phy, but not exactly the same bits so we need > a new compatible for this. > > Signed-off-by: Hans de Goede <hdegoede@redhat.com> I have almost the exact same patches in my old sun8i-otg branch. I was planning to rebase them onto the new musb patches today, but since you beat me to them, Reviewed-by: Chen-Yu Tsai <wens@csie.org> My old patches are in https://github.com/wens/linux/tree/sun8i-usb I planned on testing EHCI/OHCI first before posting anything. Regards ChenYu > --- > Documentation/devicetree/bindings/clock/sunxi.txt | 1 + > drivers/clk/sunxi/clk-usb.c | 11 +++++++++++ > 2 files changed, 12 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Tue, Jun 2, 2015 at 2:23 AM, Hans de Goede <hdegoede@redhat.com> wrote: > Add an usb_clk node for a23/a33. > > Signed-off-by: Hans de Goede <hdegoede@redhat.com> > --- > arch/arm/boot/dts/sun8i-a23-a33.dtsi | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi > index c73d1d1..44dd7155 100644 > --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi > +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi > @@ -248,6 +248,16 @@ > "mmc2_output", > "mmc2_sample"; > }; > + > + usb_clk: clk@01c200cc { > + #clock-cells = <1>; > + #reset-cells = <1>; > + compatible = "allwinner,sun8i-a23-usb-clk"; > + reg = <0x01c200cc 0x4>; > + clocks = <&osc24M>; > + clock-output-names = "usb_phy0", "usb_phy1", "hsic", > + "hsic_12m", "usb_ohci0"; Minor nitpicks: "hsic_12m" should be "hsic_12M". And maybe add the "usb_" prefix to the hsic clocks as well? Otherwise, Reviewed-by: Chen-Yu Tsai <wens@csie.org> P.S. There's a new linux-clk mailing list that these 2 patches should be sent to as well. > + }; > }; > > soc@01c00000 { > -- > 2.4.2 > > -- > You received this message because you are subscribed to the Google Groups "linux-sunxi" group. > To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com. > For more options, visit https://groups.google.com/d/optout. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Mon, Jun 01, 2015 at 08:23:27PM +0200, Hans de Goede wrote: > The usb-clk on sun8i a23 and a33 SoCs is similar to the ones found > on sun6i-a31 SoCs but instead of a 3th phy the a23 / a33 have a hsic > interface which gets enabled by almost the same bits as used on > the a31 for the 3th phy, but not exactly the same bits so we need > a new compatible for this. > > Signed-off-by: Hans de Goede <hdegoede@redhat.com> Applied with Julian spelling fix. Maxime
On Mon, Jun 01, 2015 at 08:23:28PM +0200, Hans de Goede wrote: > Add an usb_clk node for a23/a33. > > Signed-off-by: Hans de Goede <hdegoede@redhat.com> Applied with Chen-Yu's comments. Thanks! Maxime
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt index 4fa11af..8a47b77 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt @@ -67,6 +67,7 @@ Required properties: "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20 "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13 "allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31 + "allwinner,sun8i-a23-usb-clk" - for usb gates + resets on A23 "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80 "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80 diff --git a/drivers/clk/sunxi/clk-usb.c b/drivers/clk/sunxi/clk-usb.c index a86ed2f..3a25f95 100644 --- a/drivers/clk/sunxi/clk-usb.c +++ b/drivers/clk/sunxi/clk-usb.c @@ -204,6 +204,17 @@ static void __init sun6i_a31_usb_setup(struct device_node *node) } CLK_OF_DECLARE(sun6i_a31_usb, "allwinner,sun6i-a31-usb-clk", sun6i_a31_usb_setup); +static const struct usb_clk_data sun8i_a23_usb_clk_data __initconst = { + .clk_mask = BIT(16) | BIT(11) | BIT(10) | BIT(9) | BIT(8), + .reset_mask = BIT(2) | BIT(1) | BIT(0), +}; + +static void __init sun8i_a23_usb_setup(struct device_node *node) +{ + sunxi_usb_clk_setup(node, &sun8i_a23_usb_clk_data, &sun4i_a10_usb_lock); +} +CLK_OF_DECLARE(sun8i_a23_usb, "allwinner,sun8i-a23-usb-clk", sun8i_a23_usb_setup); + static const struct usb_clk_data sun9i_a80_usb_mod_data __initconst = { .clk_mask = BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1), .reset_mask = BIT(19) | BIT(18) | BIT(17),
The usb-clk on sun8i a23 and a33 SoCs is similar to the ones found on sun6i-a31 SoCs but instead of a 3th phy the a23 / a33 have a hsic interface which gets enabled by almost the same bits as used on the a31 for the 3th phy, but not exactly the same bits so we need a new compatible for this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> --- Documentation/devicetree/bindings/clock/sunxi.txt | 1 + drivers/clk/sunxi/clk-usb.c | 11 +++++++++++ 2 files changed, 12 insertions(+)