From patchwork Sat May 30 05:45:17 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 478406 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id AE4EB140F91 for ; Sat, 30 May 2015 15:46:07 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=RWGT+dNh; dkim-atps=neutral Received: from localhost ([::1]:38414 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YyZav-00071U-Je for incoming@patchwork.ozlabs.org; Sat, 30 May 2015 01:46:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38741) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YyZaH-0005zF-JR for qemu-devel@nongnu.org; Sat, 30 May 2015 01:45:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YyZaE-0000Ix-ED for qemu-devel@nongnu.org; Sat, 30 May 2015 01:45:25 -0400 Received: from mail-pa0-x229.google.com ([2607:f8b0:400e:c03::229]:32866) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YyZaE-0000Is-76 for qemu-devel@nongnu.org; Sat, 30 May 2015 01:45:22 -0400 Received: by padj3 with SMTP id j3so7040775pad.0 for ; Fri, 29 May 2015 22:45:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1PW13+zvhWYxaLVIeLm8oZ3TOtM2+y4j5lc1ItPBIRw=; b=RWGT+dNhZ5MjsHt5i6kxU3qrKUQ9OrHGB8T89z5bN8IQRKKnTNH4WpRvDhQyyMfj7L BCnN1MGNRS5+LKwyYqtOjcfHANXtdljC9VrGOVrD4Qx+v7VGLpXXNQjNlVwXBf1KVfpB k9EjvZivzCbnzay/Q0Pvl2pE+CzFsGjICer5fE0S27ViUDvzCZ06XUaSO1lN2XFZiziu 1lm9vXCJg4E6uy7pqJlw0Hyh5eVsylZ2Nsj98+bA1kxVJOx17XchdnzB1QCeljfqXj/t au7yDNWN0qjv6cT9J5qRY9+hFBuLq00ostD/utRo0IRTv5Te1KZ/OlsudI8kVUOzMrGL L0gA== X-Received: by 10.66.233.232 with SMTP id tz8mr19391233pac.77.1432964721450; Fri, 29 May 2015 22:45:21 -0700 (PDT) Received: from localhost (14-202-248-82.tpgi.com.au. [14.202.248.82]) by mx.google.com with ESMTPSA id td3sm7412263pab.46.2015.05.29.22.45.20 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 29 May 2015 22:45:20 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org, peter.crosthwaite@xilinx.com Date: Sat, 30 May 2015 15:45:17 +1000 Message-Id: X-Mailer: git-send-email 2.1.4 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c03::229 Cc: peter.maydell@linaro.org, konstanty@ieee.org, alistair23@gmail.com Subject: [Qemu-devel] [PATCH v2 2/7] STM32F2xx: Display PWM duty cycle from timer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org If correctly configured allow the STM32F2xx timer to print out the PWM duty cycle information. Signed-off-by: Alistair Francis Reviewed-by: Peter Crosthwaite --- V2: - Fix up if statement braces - Remove stm32f2xx_timer_set_alarm() call hw/timer/stm32f2xx_timer.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/timer/stm32f2xx_timer.c b/hw/timer/stm32f2xx_timer.c index ecadf9d..de4b8af 100644 --- a/hw/timer/stm32f2xx_timer.c +++ b/hw/timer/stm32f2xx_timer.c @@ -49,6 +49,15 @@ static void stm32f2xx_timer_interrupt(void *opaque) qemu_irq_pulse(s->irq); stm32f2xx_timer_set_alarm(s, s->hit_time); } + + if (s->tim_ccmr1 & (TIM_CCMR1_OC2M2 + TIM_CCMR1_OC2M1) && + !(s->tim_ccmr1 & TIM_CCMR1_OC2M0) && + s->tim_ccmr1 & TIM_CCMR1_OC2PE && + s->tim_ccer & TIM_CCER_CC2E) { + /* PWM 2 - Mode 1 */ + DB_PRINT("Duty Cycle: %d%%\n", + s->tim_ccr2 / (100 * (s->tim_psc + 1))); + } } static inline int64_t stm32f2xx_ns_to_ticks(STM32F2XXTimerState *s, int64_t t)