| Message ID | 1432418814-7438-3-git-send-email-rth@twiddle.net |
|---|---|
| State | New |
| Headers | show |
On 2015-05-23 15:06, Richard Henderson wrote: > Only exposing FPU and LLSC as the only features > supported by the translator. > > Signed-off-by: Richard Henderson <rth@twiddle.net> > --- > linux-user/elfload.c | 29 +++++++++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > > diff --git a/linux-user/elfload.c b/linux-user/elfload.c > index 0ba9706..b71e866 100644 > --- a/linux-user/elfload.c > +++ b/linux-user/elfload.c > @@ -1075,6 +1075,35 @@ static inline void elf_core_copy_regs(target_elf_gregset_t *regs, > #define USE_ELF_CORE_DUMP > #define ELF_EXEC_PAGESIZE 4096 > > +enum { > + SH_CPU_HAS_FPU = 0x0001, /* Hardware FPU support */ > + SH_CPU_HAS_P2_FLUSH_BUG = 0x0002, /* Need to flush the cache in P2 area */ > + SH_CPU_HAS_MMU_PAGE_ASSOC = 0x0004, /* SH3: TLB way selection bit support */ > + SH_CPU_HAS_DSP = 0x0008, /* SH-DSP: DSP support */ > + SH_CPU_HAS_PERF_COUNTER = 0x0010, /* Hardware performance counters */ > + SH_CPU_HAS_PTEA = 0x0020, /* PTEA register */ > + SH_CPU_HAS_LLSC = 0x0040, /* movli.l/movco.l */ > + SH_CPU_HAS_L2_CACHE = 0x0080, /* Secondary cache / URAM */ > + SH_CPU_HAS_OP32 = 0x0100, /* 32-bit instruction support */ > + SH_CPU_HAS_PTEAEX = 0x0200, /* PTE ASID Extension support */ > +}; > + > +#define ELF_HWCAP get_elf_hwcap() > + > +static uint32_t get_elf_hwcap(void) > +{ > + SuperHCPU *cpu = SUPERH_CPU(thread_cpu); > + uint32_t hwcap = 0; > + > + hwcap |= SH_CPU_HAS_FPU; > + > + if (cpu->env.features & SH_FEATURE_SH4A) { > + hwcap |= SH_CPU_HAS_LLSC; > + } > + > + return hwcap; > +} > + > #endif > > #ifdef TARGET_CRIS Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 0ba9706..b71e866 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1075,6 +1075,35 @@ static inline void elf_core_copy_regs(target_elf_gregset_t *regs, #define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE 4096 +enum { + SH_CPU_HAS_FPU = 0x0001, /* Hardware FPU support */ + SH_CPU_HAS_P2_FLUSH_BUG = 0x0002, /* Need to flush the cache in P2 area */ + SH_CPU_HAS_MMU_PAGE_ASSOC = 0x0004, /* SH3: TLB way selection bit support */ + SH_CPU_HAS_DSP = 0x0008, /* SH-DSP: DSP support */ + SH_CPU_HAS_PERF_COUNTER = 0x0010, /* Hardware performance counters */ + SH_CPU_HAS_PTEA = 0x0020, /* PTEA register */ + SH_CPU_HAS_LLSC = 0x0040, /* movli.l/movco.l */ + SH_CPU_HAS_L2_CACHE = 0x0080, /* Secondary cache / URAM */ + SH_CPU_HAS_OP32 = 0x0100, /* 32-bit instruction support */ + SH_CPU_HAS_PTEAEX = 0x0200, /* PTE ASID Extension support */ +}; + +#define ELF_HWCAP get_elf_hwcap() + +static uint32_t get_elf_hwcap(void) +{ + SuperHCPU *cpu = SUPERH_CPU(thread_cpu); + uint32_t hwcap = 0; + + hwcap |= SH_CPU_HAS_FPU; + + if (cpu->env.features & SH_FEATURE_SH4A) { + hwcap |= SH_CPU_HAS_LLSC; + } + + return hwcap; +} + #endif #ifdef TARGET_CRIS
Only exposing FPU and LLSC as the only features supported by the translator. Signed-off-by: Richard Henderson <rth@twiddle.net> --- linux-user/elfload.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+)