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[AArch64] PR target/66200 - gcc / libstdc++ TLC for weak memory models.

Message ID 555D9D3B.7040309@foss.arm.com
State New
Headers show

Commit Message

Ramana Radhakrishnan May 21, 2015, 8:54 a.m. UTC 
And here's an additional patch for the testsuite which was missed in the 
original posting.

This is a testism that's testing code generation as per 
TARGET_RELAXED_ORDERING being false and therefore needs to be adjusted 
as attached.

Ramana

PR target/66200
* g++.dg/abi/aarch64_guard1.C: Adjust testcase.
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Patch

diff --git a/gcc/testsuite/g++.dg/abi/aarch64_guard1.C b/gcc/testsuite/g++.dg/abi/aarch64_guard1.C
index ca1778b..e78f93c 100644
--- a/gcc/testsuite/g++.dg/abi/aarch64_guard1.C
+++ b/gcc/testsuite/g++.dg/abi/aarch64_guard1.C
@@ -13,5 +13,4 @@  int *foo ()
 }
 
 // { dg-final { scan-assembler _ZGVZ3foovE1x,8,8 } }
-// { dg-final { scan-tree-dump "_ZGVZ3foovE1x & 1" "original" } }
 // { dg-final { cleanup-tree-dump "original" } }