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PR target/66224 _GLIBC_READ_MEM_BARRIER

Message ID CAGWvnynDjqFzRa0OFqNew5hhuOC6Ht-ayNJ28=zi8Os50Xge-w@mail.gmail.com
State New
Headers show

Commit Message

David Edelsohn May 20, 2015, 6:40 p.m. UTC 
The current definition of _GLIBC_READ_MEM_BARRIER in libstdc++ is too
weak for an ACQUIRE FENCE, which is what it is intended to be. The
original code emitted an "isync" instead of "lwsync".

All of the guard acquire and set code needs to be cleaned up to use
GCC atomic intrinsics, but this is necessary for correctness.

Steve, any comment about the Linux part?

- David

        PR target/66224
        * config/os/aix/atomic_word.h (_GLIBCXX_READ_MEM_BARRIER): Use
        lwsync if available, not isync.
        (_GLIBCXX_WRITE_MEM_BARRIER): Use lwsync if available.
        * config/cpu/powerpc/atomic_word.h (_GLIBCXX_READ_MEM_BARRIER):
        Use lwsync if available, not isync.

Comments

Steven Munroe May 21, 2015, 3:11 p.m. UTC | #1 
On Wed, 2015-05-20 at 14:40 -0400, David Edelsohn wrote:
> The current definition of _GLIBC_READ_MEM_BARRIER in libstdc++ is too
> weak for an ACQUIRE FENCE, which is what it is intended to be. The
> original code emitted an "isync" instead of "lwsync".
> 
> All of the guard acquire and set code needs to be cleaned up to use
> GCC atomic intrinsics, but this is necessary for correctness.
> 
> Steve, any comment about the Linux part?
> 
This is correct for the PowerISA V2 (POWER4 and later) processors.

I assume the #ifdef __NO_LWSYNC guard is only set for older (ISA V1)
processors.

Thanks
diff mbox

Patch

Index: config/os/aix/atomic_word.h
===================================================================
--- config/os/aix/atomic_word.h (revision 223444)
+++ config/os/aix/atomic_word.h (working copy)
@@ -33,9 +33,16 @@ 
 typedef int _Atomic_word;

 #ifdef _ARCH_PPC
-#define _GLIBCXX_READ_MEM_BARRIER __asm __volatile ("isync":::"memory")
+
+#ifdef __NO_LWSYNC__
+#define _GLIBCXX_READ_MEM_BARRIER __asm __volatile ("sync":::"memory")
 #define _GLIBCXX_WRITE_MEM_BARRIER __asm __volatile ("sync":::"memory")
 #else
+#define _GLIBCXX_READ_MEM_BARRIER __asm __volatile ("lwsync":::"memory")
+#define _GLIBCXX_WRITE_MEM_BARRIER __asm __volatile ("lwsync":::"memory")
+#endif
+
+#else
 #define _GLIBCXX_READ_MEM_BARRIER __asm __volatile ("":::"memory")
 #define _GLIBCXX_WRITE_MEM_BARRIER __asm __volatile ("":::"memory")
 #endif
Index: config/cpu/powerpc/atomic_word.h
===================================================================
--- config/cpu/powerpc/atomic_word.h    (revision 223444)
+++ config/cpu/powerpc/atomic_word.h    (working copy)
@@ -27,10 +27,11 @@ 

 typedef int _Atomic_word;

-#define _GLIBCXX_READ_MEM_BARRIER __asm __volatile ("isync":::"memory")
 #ifdef __NO_LWSYNC__
+#define _GLIBCXX_READ_MEM_BARRIER __asm __volatile ("sync":::"memory")
 #define _GLIBCXX_WRITE_MEM_BARRIER __asm __volatile ("sync":::"memory")
 #else
+#define _GLIBCXX_READ_MEM_BARRIER __asm __volatile ("lwsync":::"memory")
 #define _GLIBCXX_WRITE_MEM_BARRIER __asm __volatile ("lwsync":::"memory")
 #endif