diff mbox

[U-Boot] arm: mx6: ddr: set fast-exit on DDR3 if pd_fast_exit specified

Message ID 1431958022-25529-1-git-send-email-tharvey@gateworks.com
State Awaiting Upstream
Delegated to: Stefano Babic
Headers show

Commit Message

Tim Harvey May 18, 2015, 2:07 p.m. UTC
Commit fa8b7d66f49f0c7bd41467fe78f6488d8af6976a introduced fast-exit support
to the MMDC however enabling it on the DDR3 got missed. Make sure we enable
it on the DDR3 as well.

Gateworks uses Micron memory as well as Winbond in MX6. We have found in
testing that we need to enable fast-exit for Winbond stability. Gateworks
boards are currently the only boards using the MX6 SPL and enabling
fast-exit mode.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
 arch/arm/cpu/armv7/mx6/ddr.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Comments

Stefano Babic May 19, 2015, 1:23 p.m. UTC | #1
On 18/05/2015 16:07, Tim Harvey wrote:
> Commit fa8b7d66f49f0c7bd41467fe78f6488d8af6976a introduced fast-exit support
> to the MMDC however enabling it on the DDR3 got missed. Make sure we enable
> it on the DDR3 as well.
> 
> Gateworks uses Micron memory as well as Winbond in MX6. We have found in
> testing that we need to enable fast-exit for Winbond stability. Gateworks
> boards are currently the only boards using the MX6 SPL and enabling
> fast-exit mode.
> 
> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
> ---

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic
diff mbox

Patch

diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 653d58e..40df2ba 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -527,7 +527,8 @@  void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 		/* MR0 */
 		val = ((tcl - 1) << 4) |	/* CAS */
 		      (1 << 8)   |		/* DLL Reset */
-		      ((twr - 3) << 9);		/* Write Recovery */
+		      ((twr - 3) << 9) |	/* Write Recovery */
+		      (sysinfo->pd_fast_exit << 12); /* Precharge PD PLL on */
 		debug("MR0 CS%d: 0x%08x\n", cs, (u32)MR(val, 0, 3, cs));
 		mmdc0->mdscr = MR(val, 0, 3, cs);
 		/* ZQ calibration */