Patchwork powerpc/85xx: Make sure lwarx hint isn't set on ppc32

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Submitter Kumar Gala
Date March 11, 2010, 5:39 a.m.
Message ID <1268285947-6114-1-git-send-email-galak@kernel.crashing.org>
Download mbox | patch
Permalink /patch/47299/
State Accepted
Commit d6ccb1f55ddf5146219707c0e71b85e3a52179b4
Headers show

Comments

Kumar Gala - March 11, 2010, 5:39 a.m.
e500v1/v2 based chips will treat any reserved field being set in an
opcode as illegal.  Thus always setting the hint in the opcode is
a bad idea.

Anton should be kept away from the powerpc opcode map.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 arch/powerpc/include/asm/ppc-opcode.h |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)
Anton Blanchard - March 13, 2010, 10:49 p.m.
Hi,

> e500v1/v2 based chips will treat any reserved field being set in an
> opcode as illegal.  Thus always setting the hint in the opcode is
> a bad idea.
> 
> Anton should be kept away from the powerpc opcode map.

Nasty bug! I promise never to touch the opcode map again :)

Acked-by: Anton Blanchard <anton@samba.org>

Anton

> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
>  arch/powerpc/include/asm/ppc-opcode.h |    6 +++---
>  1 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
> index aea7147..d553bbe 100644
> --- a/arch/powerpc/include/asm/ppc-opcode.h
> +++ b/arch/powerpc/include/asm/ppc-opcode.h
> @@ -25,7 +25,7 @@
>  #define PPC_INST_LDARX			0x7c0000a8
>  #define PPC_INST_LSWI			0x7c0004aa
>  #define PPC_INST_LSWX			0x7c00042a
> -#define PPC_INST_LWARX			0x7c000029
> +#define PPC_INST_LWARX			0x7c000028
>  #define PPC_INST_LWSYNC			0x7c2004ac
>  #define PPC_INST_LXVD2X			0x7c000698
>  #define PPC_INST_MCRXR			0x7c000400
> @@ -62,8 +62,8 @@
>  #define __PPC_T_TLB(t)	(((t) & 0x3) << 21)
>  #define __PPC_WC(w)	(((w) & 0x3) << 21)
>  /*
> - * Only use the larx hint bit on 64bit CPUs. Once we verify it doesn't have
> - * any side effects on all 32bit processors, we can do this all the time.
> + * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
> + * larx with EH set as an illegal instruction.
>   */
>  #ifdef CONFIG_PPC64
>  #define __PPC_EH(eh)	(((eh) & 0x1) << 0)
> -- 
> 1.6.0.6
> 
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev

Patch

diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index aea7147..d553bbe 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -25,7 +25,7 @@ 
 #define PPC_INST_LDARX			0x7c0000a8
 #define PPC_INST_LSWI			0x7c0004aa
 #define PPC_INST_LSWX			0x7c00042a
-#define PPC_INST_LWARX			0x7c000029
+#define PPC_INST_LWARX			0x7c000028
 #define PPC_INST_LWSYNC			0x7c2004ac
 #define PPC_INST_LXVD2X			0x7c000698
 #define PPC_INST_MCRXR			0x7c000400
@@ -62,8 +62,8 @@ 
 #define __PPC_T_TLB(t)	(((t) & 0x3) << 21)
 #define __PPC_WC(w)	(((w) & 0x3) << 21)
 /*
- * Only use the larx hint bit on 64bit CPUs. Once we verify it doesn't have
- * any side effects on all 32bit processors, we can do this all the time.
+ * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
+ * larx with EH set as an illegal instruction.
  */
 #ifdef CONFIG_PPC64
 #define __PPC_EH(eh)	(((eh) & 0x1) << 0)