[i386] : Macroize mul{,v} patterns some more

Message ID	CAFULd4aC+fOM+pwAF3PtAAjHCxcAv9E=DmSnB4m-7rrLyMr_iw@mail.gmail.com
State	New
Headers	show Return-Path: <gcc-patches-return-397821-incoming=patchwork.ozlabs.org@gcc.gnu.org> DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:date:message-id:subject:from:to:cc:content-type; q=dns; s=default; b=bBfUcKU7WOao/Zj8V9mhJSkykL8d+PIVIYjykLiuhua lU1R+2/hRK/1Ay3qo5ms806fI4yYMzUbdWr+tnRUcfBQ7aBBK8wjWqHgKq9iX8h2 Dd7iVEFskXH71tI7xWqqu+zyGOHQdKc80LgoZAbnjjoQlSYypFxyt2IAVH2osA2E = Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk Sender: gcc-patches-owner@gcc.gnu.org MIME-Version: 1.0 Date: Wed, 13 May 2015 20:04:09 +0200 Message-ID: <CAFULd4aC+fOM+pwAF3PtAAjHCxcAv9E=DmSnB4m-7rrLyMr_iw@mail.gmail.com> Subject: [PATCH, i386]: Macroize mul{,v} patterns some more From: Uros Bizjak <ubizjak@gmail.com> To: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org> Cc: Jakub Jelinek <jakub@redhat.com> Content-Type: multipart/mixed; boundary=047d7b675af6120cd00515fa7000

Index: config/i386/i386.md =================================================================== --- config/i386/i386.md (revision 223117) +++ config/i386/i386.md (working copy) @@ -6477,12 +6477,22 @@ ;; IMUL reg32/64, mem32/64 Direct ;; ;; On BDVER1, all above IMULs use DirectPath +;; +;; On AMDFAM10 +;; IMUL reg16, reg16, imm8 VectorPath +;; IMUL reg16, mem16, imm8 VectorPath +;; IMUL reg16, reg16, imm16 VectorPath +;; IMUL reg16, mem16, imm16 VectorPath +;; IMUL reg16, reg16 Direct +;; IMUL reg16, mem16 Direct +;; +;; On BDVER1, all HI MULs use DoublePath (define_insn "*mul<mode>3_1" - [(set (match_operand:SWI48 0 "register_operand" "=r,r,r") - (mult:SWI48 - (match_operand:SWI48 1 "nonimmediate_operand" "%rm,rm,0") - (match_operand:SWI48 2 "<general_operand>" "K,<i>,mr"))) + [(set (match_operand:SWIM248 0 "register_operand" "=r,r,r") + (mult:SWIM248 + (match_operand:SWIM248 1 "nonimmediate_operand" "%rm,rm,0") + (match_operand:SWIM248 2 "<general_operand>" "K,<i>,mr"))) (clobber (reg:CC FLAGS_REG))] "!(MEM_P (operands[1]) && MEM_P (operands[2]))" "@ @@ -6497,15 +6507,21 @@ (eq_attr "alternative" "1") (const_string "vector") (and (eq_attr "alternative" "2") - (match_operand 1 "memory_operand")) + (ior (match_test "<MODE>mode == HImode") + (match_operand 1 "memory_operand"))) (const_string "vector")] (const_string "direct"))) (set (attr "amdfam10_decode") (cond [(and (eq_attr "alternative" "0,1") - (match_operand 1 "memory_operand")) + (ior (match_test "<MODE>mode == HImode") + (match_operand 1 "memory_operand"))) (const_string "vector")] (const_string "direct"))) - (set_attr "bdver1_decode" "direct") + (set (attr "bdver1_decode") + (if_then_else + (match_test "<MODE>mode == HImode") + (const_string "double") + (const_string "direct"))) (set_attr "mode" "<MODE>")]) (define_insn "*mulsi3_1_zext" @@ -6539,42 +6555,6 @@ (set_attr "bdver1_decode" "direct") (set_attr "mode" "SI")]) -;; On AMDFAM10 -;; IMUL reg16, reg16, imm8 VectorPath -;; IMUL reg16, mem16, imm8 VectorPath -;; IMUL reg16, reg16, imm16 VectorPath -;; IMUL reg16, mem16, imm16 VectorPath -;; IMUL reg16, reg16 Direct -;; IMUL reg16, mem16 Direct -;; -;; On BDVER1, all HI MULs use DoublePath - -(define_insn "*mulhi3_1" - [(set (match_operand:HI 0 "register_operand" "=r,r,r") - (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,rm,0") - (match_operand:HI 2 "general_operand" "K,n,mr"))) - (clobber (reg:CC FLAGS_REG))] - "TARGET_HIMODE_MATH - && !(MEM_P (operands[1]) && MEM_P (operands[2]))" - "@ - imul{w}\t{%2, %1, %0|%0, %1, %2} - imul{w}\t{%2, %1, %0|%0, %1, %2} - imul{w}\t{%2, %0|%0, %2}" - [(set_attr "type" "imul") - (set_attr "prefix_0f" "0,0,1") - (set (attr "athlon_decode") - (cond [(eq_attr "cpu" "athlon") - (const_string "vector") - (eq_attr "alternative" "1,2") - (const_string "vector")] - (const_string "direct"))) - (set (attr "amdfam10_decode") - (cond [(eq_attr "alternative" "0,1") - (const_string "vector")] - (const_string "direct"))) - (set_attr "bdver1_decode" "double") - (set_attr "mode" "HI")]) - ;;On AMDFAM10 and BDVER1 ;; MUL reg8 Direct ;; MUL mem8 Direct @@ -6628,8 +6608,7 @@ (sign_extend:<DWI> (match_operand:SWI48 1 "nonimmediate_operand" "%rm,0")) (sign_extend:<DWI> - (match_operand:SWI48 2 "<general_sext_operand>" - "We,mr"))) + (match_operand:SWI48 2 "x86_64_sext_operand" "We,mr"))) (sign_extend:<DWI> (mult:SWI48 (match_dup 1) (match_dup 2))))) (set (match_operand:SWI48 0 "register_operand" "=r,r") @@ -6657,49 +6636,13 @@ (set_attr "bdver1_decode" "direct") (set_attr "mode" "<MODE>")]) -(define_insn "*mulv<mode>4_1" - [(set (reg:CCO FLAGS_REG) - (eq:CCO (mult:<DWI> - (sign_extend:<DWI> - (match_operand:SWI48 1 "nonimmediate_operand" "rm,rm")) - (match_operand:<DWI> 3 "const_int_operand" "K,i")) - (sign_extend:<DWI> - (mult:SWI48 (match_dup 1) - (match_operand:SWI48 2 - "x86_64_immediate_operand" "K,<i>"))))) - (set (match_operand:SWI48 0 "register_operand" "=r,r") - (mult:SWI48 (match_dup 1) (match_dup 2)))] - "!(MEM_P (operands[1]) && MEM_P (operands[2])) - && CONST_INT_P (operands[2]) - && INTVAL (operands[2]) == INTVAL (operands[3])" - "imul{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "type" "imul") - (set (attr "athlon_decode") - (cond [(eq_attr "cpu" "athlon") - (const_string "vector") - (eq_attr "alternative" "1") - (const_string "vector")] - (const_string "direct"))) - (set (attr "amdfam10_decode") - (cond [(match_operand 1 "memory_operand") - (const_string "vector")] - (const_string "direct"))) - (set_attr "bdver1_decode" "direct") - (set_attr "mode" "<MODE>") - (set (attr "length_immediate") - (cond [(eq_attr "alternative" "0") - (const_string "1") - (match_test "<MODE_SIZE> == 8") - (const_string "4")] - (const_string "<MODE_SIZE>")))]) - (define_insn "*mulvhi4" [(set (reg:CCO FLAGS_REG) (eq:CCO (mult:SI (sign_extend:SI - (match_operand:HI 1 "nonimmediate_operand" "0")) + (match_operand:HI 1 "nonimmediate_operand" "%0")) (sign_extend:SI - (match_operand:HI 2 "general_operand" "mr"))) + (match_operand:HI 2 "nonimmediate_operand" "mr"))) (sign_extend:SI (mult:HI (match_dup 1) (match_dup 2))))) (set (match_operand:HI 0 "register_operand" "=r") @@ -6713,37 +6656,51 @@ (set_attr "bdver1_decode" "double") (set_attr "mode" "HI")]) -(define_insn "*mulvhi4_1" +(define_insn "*mulv<mode>4_1" [(set (reg:CCO FLAGS_REG) - (eq:CCO (mult:SI - (sign_extend:SI - (match_operand:HI 1 "nonimmediate_operand" "rm,rm")) - (match_operand:SI 3 "const_int_operand" "K,i")) - (sign_extend:SI - (mult:HI (match_dup 1) - (match_operand:HI 2 - "x86_64_immediate_operand" "K,n"))))) - (set (match_operand:HI 0 "register_operand" "=r,r") - (mult:HI (match_dup 1) (match_dup 2)))] + (eq:CCO (mult:<DWI> + (sign_extend:<DWI> + (match_operand:SWI248 1 "nonimmediate_operand" "rm,rm")) + (match_operand:<DWI> 3 "const_int_operand" "K,i")) + (sign_extend:<DWI> + (mult:SWI248 (match_dup 1) + (match_operand:SWI248 2 + "<immediate_operand>" "K,<i>"))))) + (set (match_operand:SWI248 0 "register_operand" "=r,r") + (mult:SWI248 (match_dup 1) (match_dup 2)))] "!(MEM_P (operands[1]) && MEM_P (operands[2])) && CONST_INT_P (operands[2]) && INTVAL (operands[2]) == INTVAL (operands[3])" - "imul{w}\t{%2, %1, %0|%0, %1, %2}" + "imul{<imodesuffix>}\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "imul") - (set_attr "prefix_0f" "0") + (set (attr "prefix_0f") + (if_then_else + (match_test "<MODE>mode == HImode") + (const_string "0") + (const_string "*"))) (set (attr "athlon_decode") (cond [(eq_attr "cpu" "athlon") (const_string "vector") (eq_attr "alternative" "1") (const_string "vector")] (const_string "direct"))) - (set_attr "amdfam10_decode" "vector") - (set_attr "bdver1_decode" "double") - (set_attr "mode" "HI") + (set (attr "amdfam10_decode") + (cond [(ior (match_test "<MODE>mode == HImode") + (match_operand 1 "memory_operand")) + (const_string "vector")] + (const_string "direct"))) + (set (attr "bdver1_decode") + (if_then_else + (match_test "<MODE>mode == HImode") + (const_string "double") + (const_string "direct"))) + (set_attr "mode" "<MODE>") (set (attr "length_immediate") (cond [(eq_attr "alternative" "0") - (const_string "1")] - (const_string "2")))]) + (const_string "1") + (match_test "<MODE_SIZE> == 8") + (const_string "4")] + (const_string "<MODE_SIZE>")))]) (define_expand "umulv<mode>4" [(parallel [(set (reg:CCO FLAGS_REG)

[i386] : Macroize mul{,v} patterns some more

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