diff mbox

[3/6] arm64: tegra: Add Tegra210 support

Message ID 1431529065-20128-3-git-send-email-thierry.reding@gmail.com
State Accepted, archived
Headers show

Commit Message

Thierry Reding May 13, 2015, 2:57 p.m. UTC 
From: Thierry Reding <treding@nvidia.com>

NVIDIA Tegra210 (also known as Tegra X1) has four Cortex-A57 and four
Cortex-A53 CPUs. Compared to Tegra124 and Tegra132 it comes with a 256-
core Maxwell GPU. It supports processing videos of up to 4K resolutions
at 60 fps (H.265, VP9, H.264).

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 arch/arm64/Kconfig                       |   9 +
 arch/arm64/boot/dts/nvidia/tegra210.dtsi | 998 +++++++++++++++++++++++++++++++
 2 files changed, 1007 insertions(+)
 create mode 100644 arch/arm64/boot/dts/nvidia/tegra210.dtsi

Comments

Catalin Marinas May 13, 2015, 5:11 p.m. UTC | #1 
On Wed, May 13, 2015 at 04:57:42PM +0200, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> NVIDIA Tegra210 (also known as Tegra X1) has four Cortex-A57 and four
> Cortex-A53 CPUs. Compared to Tegra124 and Tegra132 it comes with a 256-
> core Maxwell GPU. It supports processing videos of up to 4K resolutions
> at 60 fps (H.265, VP9, H.264).
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  arch/arm64/Kconfig                       |   9 +
>  arch/arm64/boot/dts/nvidia/tegra210.dtsi | 998 +++++++++++++++++++++++++++++++
>  2 files changed, 1007 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/nvidia/tegra210.dtsi
> 
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index 7796af4b1d6f..bfdf064ada66 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -225,6 +225,15 @@ config ARCH_TEGRA_132_SOC
>  	  but contains an NVIDIA Denver CPU complex in place of
>  	  Tegra124's "4+1" Cortex-A15 CPU complex.
>  
> +config ARCH_TEGRA_210_SOC
> +	bool "NVIDIA Tegra210 SoC"
> +	depends on ARCH_TEGRA
> +	select PINCTRL_TEGRA210
> +	select USB_ULPI if USB_PHY
> +	select USB_ULPI_VIEWPORT if USB_PHY
> +	help
> +	  Enable support for the NVIDIA Tegra210 SoC.
> +

The previous ARCH_TEGRA_132_SOC escaped me. Do we need all these
ARCH_TEGRA_*_SOC entries? Can we not have per-driver Kconfig options?
For example, ARCH_TEGRA_132_SOC seems to be only used in
drivers/clk/tegra, a specific Kconfig entry in there would suffice.
Thierry Reding May 15, 2015, 10:19 a.m. UTC | #2 
On Wed, May 13, 2015 at 06:11:15PM +0100, Catalin Marinas wrote:
> On Wed, May 13, 2015 at 04:57:42PM +0200, Thierry Reding wrote:
> > From: Thierry Reding <treding@nvidia.com>
> > 
> > NVIDIA Tegra210 (also known as Tegra X1) has four Cortex-A57 and four
> > Cortex-A53 CPUs. Compared to Tegra124 and Tegra132 it comes with a 256-
> > core Maxwell GPU. It supports processing videos of up to 4K resolutions
> > at 60 fps (H.265, VP9, H.264).
> > 
> > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > ---
> >  arch/arm64/Kconfig                       |   9 +
> >  arch/arm64/boot/dts/nvidia/tegra210.dtsi | 998 +++++++++++++++++++++++++++++++
> >  2 files changed, 1007 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/nvidia/tegra210.dtsi
> > 
> > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> > index 7796af4b1d6f..bfdf064ada66 100644
> > --- a/arch/arm64/Kconfig
> > +++ b/arch/arm64/Kconfig
> > @@ -225,6 +225,15 @@ config ARCH_TEGRA_132_SOC
> >  	  but contains an NVIDIA Denver CPU complex in place of
> >  	  Tegra124's "4+1" Cortex-A15 CPU complex.
> >  
> > +config ARCH_TEGRA_210_SOC
> > +	bool "NVIDIA Tegra210 SoC"
> > +	depends on ARCH_TEGRA
> > +	select PINCTRL_TEGRA210
> > +	select USB_ULPI if USB_PHY
> > +	select USB_ULPI_VIEWPORT if USB_PHY
> > +	help
> > +	  Enable support for the NVIDIA Tegra210 SoC.
> > +
> 
> The previous ARCH_TEGRA_132_SOC escaped me. Do we need all these
> ARCH_TEGRA_*_SOC entries? Can we not have per-driver Kconfig options?
> For example, ARCH_TEGRA_132_SOC seems to be only used in
> drivers/clk/tegra, a specific Kconfig entry in there would suffice.

There are actually a couple of other places where this will be used in
subsequent patches (e.g. memory controller driver). The idea behind
having these is that each one of them is used to enable the essentials
out of the box, so that people don't have to go and enable a bunch of
driver-specific Kconfig options just to get a kernel configuration that
can actually boot.

This is also useful for integrators since they can simply omit all SoC
generations that they're not interested in. Having a per-SoC option
provides an easy way of doing so.

Thierry
Catalin Marinas May 19, 2015, 2:52 p.m. UTC | #3 
On Fri, May 15, 2015 at 12:19:16PM +0200, Thierry Reding wrote:
> On Wed, May 13, 2015 at 06:11:15PM +0100, Catalin Marinas wrote:
> > On Wed, May 13, 2015 at 04:57:42PM +0200, Thierry Reding wrote:
> > > From: Thierry Reding <treding@nvidia.com>
> > > 
> > > NVIDIA Tegra210 (also known as Tegra X1) has four Cortex-A57 and four
> > > Cortex-A53 CPUs. Compared to Tegra124 and Tegra132 it comes with a 256-
> > > core Maxwell GPU. It supports processing videos of up to 4K resolutions
> > > at 60 fps (H.265, VP9, H.264).
> > > 
> > > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > > ---
> > >  arch/arm64/Kconfig                       |   9 +
> > >  arch/arm64/boot/dts/nvidia/tegra210.dtsi | 998 +++++++++++++++++++++++++++++++
> > >  2 files changed, 1007 insertions(+)
> > >  create mode 100644 arch/arm64/boot/dts/nvidia/tegra210.dtsi
> > > 
> > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> > > index 7796af4b1d6f..bfdf064ada66 100644
> > > --- a/arch/arm64/Kconfig
> > > +++ b/arch/arm64/Kconfig
> > > @@ -225,6 +225,15 @@ config ARCH_TEGRA_132_SOC
> > >  	  but contains an NVIDIA Denver CPU complex in place of
> > >  	  Tegra124's "4+1" Cortex-A15 CPU complex.
> > >  
> > > +config ARCH_TEGRA_210_SOC
> > > +	bool "NVIDIA Tegra210 SoC"
> > > +	depends on ARCH_TEGRA
> > > +	select PINCTRL_TEGRA210
> > > +	select USB_ULPI if USB_PHY
> > > +	select USB_ULPI_VIEWPORT if USB_PHY
> > > +	help
> > > +	  Enable support for the NVIDIA Tegra210 SoC.
> > > +
> > 
> > The previous ARCH_TEGRA_132_SOC escaped me. Do we need all these
> > ARCH_TEGRA_*_SOC entries? Can we not have per-driver Kconfig options?
> > For example, ARCH_TEGRA_132_SOC seems to be only used in
> > drivers/clk/tegra, a specific Kconfig entry in there would suffice.
> 
> There are actually a couple of other places where this will be used in
> subsequent patches (e.g. memory controller driver). The idea behind
> having these is that each one of them is used to enable the essentials
> out of the box, so that people don't have to go and enable a bunch of
> driver-specific Kconfig options just to get a kernel configuration that
> can actually boot.

We debated whether to have ARCH_* options at all on arm64 and we settled
for the middle ground - only add them for SoC families, not individual
SoCs. As for the kernel configuration that actually boots, we want the
arm64 defconfig to include all the supported SoCs and drivers (though
longer term I'd like to see more drivers built as modules by default).

> This is also useful for integrators since they can simply omit all SoC
> generations that they're not interested in. Having a per-SoC option
> provides an easy way of doing so.

The integrators could just select a SoC family and trim down unwanted
options, I don't think they rely on the kernel defconfig for a final
product. If this becomes an issue, I would rather have per-SoC
defconfigs than lots of Kconfig entries.
Thierry Reding May 19, 2015, 3:17 p.m. UTC | #4 
On Tue, May 19, 2015 at 03:52:11PM +0100, Catalin Marinas wrote:
> On Fri, May 15, 2015 at 12:19:16PM +0200, Thierry Reding wrote:
> > On Wed, May 13, 2015 at 06:11:15PM +0100, Catalin Marinas wrote:
> > > On Wed, May 13, 2015 at 04:57:42PM +0200, Thierry Reding wrote:
> > > > From: Thierry Reding <treding@nvidia.com>
> > > > 
> > > > NVIDIA Tegra210 (also known as Tegra X1) has four Cortex-A57 and four
> > > > Cortex-A53 CPUs. Compared to Tegra124 and Tegra132 it comes with a 256-
> > > > core Maxwell GPU. It supports processing videos of up to 4K resolutions
> > > > at 60 fps (H.265, VP9, H.264).
> > > > 
> > > > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > > > ---
> > > >  arch/arm64/Kconfig                       |   9 +
> > > >  arch/arm64/boot/dts/nvidia/tegra210.dtsi | 998 +++++++++++++++++++++++++++++++
> > > >  2 files changed, 1007 insertions(+)
> > > >  create mode 100644 arch/arm64/boot/dts/nvidia/tegra210.dtsi
> > > > 
> > > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> > > > index 7796af4b1d6f..bfdf064ada66 100644
> > > > --- a/arch/arm64/Kconfig
> > > > +++ b/arch/arm64/Kconfig
> > > > @@ -225,6 +225,15 @@ config ARCH_TEGRA_132_SOC
> > > >  	  but contains an NVIDIA Denver CPU complex in place of
> > > >  	  Tegra124's "4+1" Cortex-A15 CPU complex.
> > > >  
> > > > +config ARCH_TEGRA_210_SOC
> > > > +	bool "NVIDIA Tegra210 SoC"
> > > > +	depends on ARCH_TEGRA
> > > > +	select PINCTRL_TEGRA210
> > > > +	select USB_ULPI if USB_PHY
> > > > +	select USB_ULPI_VIEWPORT if USB_PHY
> > > > +	help
> > > > +	  Enable support for the NVIDIA Tegra210 SoC.
> > > > +
> > > 
> > > The previous ARCH_TEGRA_132_SOC escaped me. Do we need all these
> > > ARCH_TEGRA_*_SOC entries? Can we not have per-driver Kconfig options?
> > > For example, ARCH_TEGRA_132_SOC seems to be only used in
> > > drivers/clk/tegra, a specific Kconfig entry in there would suffice.
> > 
> > There are actually a couple of other places where this will be used in
> > subsequent patches (e.g. memory controller driver). The idea behind
> > having these is that each one of them is used to enable the essentials
> > out of the box, so that people don't have to go and enable a bunch of
> > driver-specific Kconfig options just to get a kernel configuration that
> > can actually boot.
> 
> We debated whether to have ARCH_* options at all on arm64 and we settled
> for the middle ground - only add them for SoC families, not individual
> SoCs. As for the kernel configuration that actually boots, we want the
> arm64 defconfig to include all the supported SoCs and drivers (though
> longer term I'd like to see more drivers built as modules by default).
> 
> > This is also useful for integrators since they can simply omit all SoC
> > generations that they're not interested in. Having a per-SoC option
> > provides an easy way of doing so.
> 
> The integrators could just select a SoC family and trim down unwanted
> options, I don't think they rely on the kernel defconfig for a final
> product. If this becomes an issue, I would rather have per-SoC
> defconfigs than lots of Kconfig entries.

I understand the desire to start with a clean plate on a new
architecture, but Tegra has worked like this for the past 5 years and
it's worked out really well for us. So I'm reluctant to introduce these
inconsistencies merely because 64-bit ARM now lives in a different
directory.

Are you concerned about arch/arm64/Kconfig growing wild? If so we could
easily move these configuration options outside to something like
drivers/soc/tegra/Kconfig. While at it, we could move existing options
from arch/arm/mach-tegra over to that as well.

Thierry
Catalin Marinas May 22, 2015, 1:38 p.m. UTC | #5 
On Tue, May 19, 2015 at 05:17:42PM +0200, Thierry Reding wrote:
> On Tue, May 19, 2015 at 03:52:11PM +0100, Catalin Marinas wrote:
> > On Fri, May 15, 2015 at 12:19:16PM +0200, Thierry Reding wrote:
> > > On Wed, May 13, 2015 at 06:11:15PM +0100, Catalin Marinas wrote:
> > > > On Wed, May 13, 2015 at 04:57:42PM +0200, Thierry Reding wrote:
> > > > > From: Thierry Reding <treding@nvidia.com>
> > > > > 
> > > > > NVIDIA Tegra210 (also known as Tegra X1) has four Cortex-A57 and four
> > > > > Cortex-A53 CPUs. Compared to Tegra124 and Tegra132 it comes with a 256-
> > > > > core Maxwell GPU. It supports processing videos of up to 4K resolutions
> > > > > at 60 fps (H.265, VP9, H.264).
> > > > > 
> > > > > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > > > > ---
> > > > >  arch/arm64/Kconfig                       |   9 +
> > > > >  arch/arm64/boot/dts/nvidia/tegra210.dtsi | 998 +++++++++++++++++++++++++++++++
> > > > >  2 files changed, 1007 insertions(+)
> > > > >  create mode 100644 arch/arm64/boot/dts/nvidia/tegra210.dtsi
> > > > > 
> > > > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> > > > > index 7796af4b1d6f..bfdf064ada66 100644
> > > > > --- a/arch/arm64/Kconfig
> > > > > +++ b/arch/arm64/Kconfig
> > > > > @@ -225,6 +225,15 @@ config ARCH_TEGRA_132_SOC
> > > > >  	  but contains an NVIDIA Denver CPU complex in place of
> > > > >  	  Tegra124's "4+1" Cortex-A15 CPU complex.
> > > > >  
> > > > > +config ARCH_TEGRA_210_SOC
> > > > > +	bool "NVIDIA Tegra210 SoC"
> > > > > +	depends on ARCH_TEGRA
> > > > > +	select PINCTRL_TEGRA210
> > > > > +	select USB_ULPI if USB_PHY
> > > > > +	select USB_ULPI_VIEWPORT if USB_PHY
> > > > > +	help
> > > > > +	  Enable support for the NVIDIA Tegra210 SoC.
> > > > > +
> > > > 
> > > > The previous ARCH_TEGRA_132_SOC escaped me. Do we need all these
> > > > ARCH_TEGRA_*_SOC entries? Can we not have per-driver Kconfig options?
> > > > For example, ARCH_TEGRA_132_SOC seems to be only used in
> > > > drivers/clk/tegra, a specific Kconfig entry in there would suffice.
> > > 
> > > There are actually a couple of other places where this will be used in
> > > subsequent patches (e.g. memory controller driver). The idea behind
> > > having these is that each one of them is used to enable the essentials
> > > out of the box, so that people don't have to go and enable a bunch of
> > > driver-specific Kconfig options just to get a kernel configuration that
> > > can actually boot.
> > 
> > We debated whether to have ARCH_* options at all on arm64 and we settled
> > for the middle ground - only add them for SoC families, not individual
> > SoCs. As for the kernel configuration that actually boots, we want the
> > arm64 defconfig to include all the supported SoCs and drivers (though
> > longer term I'd like to see more drivers built as modules by default).
> > 
> > > This is also useful for integrators since they can simply omit all SoC
> > > generations that they're not interested in. Having a per-SoC option
> > > provides an easy way of doing so.
> > 
> > The integrators could just select a SoC family and trim down unwanted
> > options, I don't think they rely on the kernel defconfig for a final
> > product. If this becomes an issue, I would rather have per-SoC
> > defconfigs than lots of Kconfig entries.
> 
> I understand the desire to start with a clean plate on a new
> architecture, but Tegra has worked like this for the past 5 years and
> it's worked out really well for us. So I'm reluctant to introduce these
> inconsistencies merely because 64-bit ARM now lives in a different
> directory.

That's a good time to start cleaning this up, especially since we
mandate single image from the beginning.

> Are you concerned about arch/arm64/Kconfig growing wild? If so we could
> easily move these configuration options outside to something like
> drivers/soc/tegra/Kconfig. While at it, we could move existing options
> from arch/arm/mach-tegra over to that as well.

I think the whole ARCH_TEGRA_*_SOC approach is wrong. You don't bother
introducing Kconfig entries for individual drivers but instead add an
obj-*_SOC in various Makefiles under drivers/. If we ever get to a point
where we can build (part of) the SoCs as modules (and I'm not talking
about kernels shipped with end products but those distro kernel
targeting development boards), we have to go back and add such Kconfig
entries for specific drivers.

So if you do it properly from the beginning with per-driver Kconfig
entry, I no longer see the point of an ARCH_TEGRA_*_SOC option. It may
be more convenient for people building end products but they should know
better what components are required, defconfig is rarely meant for them.

I'm looking forward to a patch removing ARCH_TEGRA_132_SOC as well (you
can keep the 32-bit arm options if you'd like).
Thierry Reding May 22, 2015, 3:05 p.m. UTC | #6 
On Fri, May 22, 2015 at 02:38:00PM +0100, Catalin Marinas wrote:
> On Tue, May 19, 2015 at 05:17:42PM +0200, Thierry Reding wrote:
> > On Tue, May 19, 2015 at 03:52:11PM +0100, Catalin Marinas wrote:
> > > On Fri, May 15, 2015 at 12:19:16PM +0200, Thierry Reding wrote:
> > > > On Wed, May 13, 2015 at 06:11:15PM +0100, Catalin Marinas wrote:
> > > > > On Wed, May 13, 2015 at 04:57:42PM +0200, Thierry Reding wrote:
> > > > > > From: Thierry Reding <treding@nvidia.com>
> > > > > > 
> > > > > > NVIDIA Tegra210 (also known as Tegra X1) has four Cortex-A57 and four
> > > > > > Cortex-A53 CPUs. Compared to Tegra124 and Tegra132 it comes with a 256-
> > > > > > core Maxwell GPU. It supports processing videos of up to 4K resolutions
> > > > > > at 60 fps (H.265, VP9, H.264).
> > > > > > 
> > > > > > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > > > > > ---
> > > > > >  arch/arm64/Kconfig                       |   9 +
> > > > > >  arch/arm64/boot/dts/nvidia/tegra210.dtsi | 998 +++++++++++++++++++++++++++++++
> > > > > >  2 files changed, 1007 insertions(+)
> > > > > >  create mode 100644 arch/arm64/boot/dts/nvidia/tegra210.dtsi
> > > > > > 
> > > > > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> > > > > > index 7796af4b1d6f..bfdf064ada66 100644
> > > > > > --- a/arch/arm64/Kconfig
> > > > > > +++ b/arch/arm64/Kconfig
> > > > > > @@ -225,6 +225,15 @@ config ARCH_TEGRA_132_SOC
> > > > > >  	  but contains an NVIDIA Denver CPU complex in place of
> > > > > >  	  Tegra124's "4+1" Cortex-A15 CPU complex.
> > > > > >  
> > > > > > +config ARCH_TEGRA_210_SOC
> > > > > > +	bool "NVIDIA Tegra210 SoC"
> > > > > > +	depends on ARCH_TEGRA
> > > > > > +	select PINCTRL_TEGRA210
> > > > > > +	select USB_ULPI if USB_PHY
> > > > > > +	select USB_ULPI_VIEWPORT if USB_PHY
> > > > > > +	help
> > > > > > +	  Enable support for the NVIDIA Tegra210 SoC.
> > > > > > +
> > > > > 
> > > > > The previous ARCH_TEGRA_132_SOC escaped me. Do we need all these
> > > > > ARCH_TEGRA_*_SOC entries? Can we not have per-driver Kconfig options?
> > > > > For example, ARCH_TEGRA_132_SOC seems to be only used in
> > > > > drivers/clk/tegra, a specific Kconfig entry in there would suffice.
> > > > 
> > > > There are actually a couple of other places where this will be used in
> > > > subsequent patches (e.g. memory controller driver). The idea behind
> > > > having these is that each one of them is used to enable the essentials
> > > > out of the box, so that people don't have to go and enable a bunch of
> > > > driver-specific Kconfig options just to get a kernel configuration that
> > > > can actually boot.
> > > 
> > > We debated whether to have ARCH_* options at all on arm64 and we settled
> > > for the middle ground - only add them for SoC families, not individual
> > > SoCs. As for the kernel configuration that actually boots, we want the
> > > arm64 defconfig to include all the supported SoCs and drivers (though
> > > longer term I'd like to see more drivers built as modules by default).
> > > 
> > > > This is also useful for integrators since they can simply omit all SoC
> > > > generations that they're not interested in. Having a per-SoC option
> > > > provides an easy way of doing so.
> > > 
> > > The integrators could just select a SoC family and trim down unwanted
> > > options, I don't think they rely on the kernel defconfig for a final
> > > product. If this becomes an issue, I would rather have per-SoC
> > > defconfigs than lots of Kconfig entries.
> > 
> > I understand the desire to start with a clean plate on a new
> > architecture, but Tegra has worked like this for the past 5 years and
> > it's worked out really well for us. So I'm reluctant to introduce these
> > inconsistencies merely because 64-bit ARM now lives in a different
> > directory.
> 
> That's a good time to start cleaning this up, especially since we
> mandate single image from the beginning.
> 
> > Are you concerned about arch/arm64/Kconfig growing wild? If so we could
> > easily move these configuration options outside to something like
> > drivers/soc/tegra/Kconfig. While at it, we could move existing options
> > from arch/arm/mach-tegra over to that as well.
> 
> I think the whole ARCH_TEGRA_*_SOC approach is wrong. You don't bother
> introducing Kconfig entries for individual drivers but instead add an
> obj-*_SOC in various Makefiles under drivers/. If we ever get to a point
> where we can build (part of) the SoCs as modules (and I'm not talking
> about kernels shipped with end products but those distro kernel
> targeting development boards), we have to go back and add such Kconfig
> entries for specific drivers.

We can cross that bridge when we get to it. Currently we only use them
in the fashion you describe for essential drivers that can't be built as
modules. If that ever changes we can easily add the Kconfig entry. This
isn't as much churn as you make it out to be, after all if the Kconfig
entry already existed we'd still have to change it from bool to tristate
to make them build as modules.

Another situation in which we use these Kconfig symbols is for drivers
that have an own Kconfig entry but that support more than one SoC
generation so that we automatically strip support for SoCs for which
support isn't selected. This is especially useful to avoid building code
that will only ever work on 32-bit Tegra on 64-bit builds.

> So if you do it properly from the beginning with per-driver Kconfig
> entry, I no longer see the point of an ARCH_TEGRA_*_SOC option. It may
> be more convenient for people building end products but they should know
> better what components are required, defconfig is rarely meant for them.

Your proposal also means that we'll have to go and add separate Kconfig
entries for each SoC generation that a driver supports so that the SoC
specific bits can be disabled.

So in order to get rid of one per-SoC Kconfig entry you'd prefer us to
add per-SoC options per driver? Don't you think that's going to make
things worse rather than improve them?

There are currently three drivers (off the top of my head) where we do
this and each of them supports five existing generations plus the new
Tegra210. So rather than having six symbols to select SoC generation
support we'd be needing 18, and that's only counting existing drivers.

> I'm looking forward to a patch removing ARCH_TEGRA_132_SOC as well (you
> can keep the 32-bit arm options if you'd like).

Given the above, will you reconsider? I already proposed that we move
these under drivers/soc/tegra (though I'd like to hear Arnd's opinion on
that first), that way you wouldn't have to concern yourself with them.

Thierry
Catalin Marinas May 22, 2015, 3:33 p.m. UTC | #7 
On Fri, May 22, 2015 at 05:05:16PM +0200, Thierry Reding wrote:
> On Fri, May 22, 2015 at 02:38:00PM +0100, Catalin Marinas wrote:
> > So if you do it properly from the beginning with per-driver Kconfig
> > entry, I no longer see the point of an ARCH_TEGRA_*_SOC option. It may
> > be more convenient for people building end products but they should know
> > better what components are required, defconfig is rarely meant for them.
> 
> Your proposal also means that we'll have to go and add separate Kconfig
> entries for each SoC generation that a driver supports so that the SoC
> specific bits can be disabled.
> 
> So in order to get rid of one per-SoC Kconfig entry you'd prefer us to
> add per-SoC options per driver? Don't you think that's going to make
> things worse rather than improve them?
> 
> There are currently three drivers (off the top of my head) where we do
> this and each of them supports five existing generations plus the new
> Tegra210. So rather than having six symbols to select SoC generation
> support we'd be needing 18, and that's only counting existing drivers.

That's not what I meant. For example, you have a clk-tegra124.c file
built for two SoCs already and there may be more coming. Instead of
multiple obj-y of the same file, just add the entry below to
drivers/clk/tegra/Kconfig:

config CLK_TEGRA124
	bool "NVIDIA Tegra 124 clock"
	depends on ARCH_TEGRA_124_SOC || (ARM64 && ARCH_TEGRA)
	default y
	help
	  Used on Tegra 124, 132 etc.
	  ...

Note that I preserved the 124_SOC dependency for the 32-bit arm case.
But for arm64, just make it dependent on ARCH_TEGRA.

Once done, the Makefile only needs a single entry:

obj-$(CONFIG_TEGRA124) += clk-tegra124.o
Stephen Warren May 22, 2015, 3:37 p.m. UTC | #8 
On 05/22/2015 07:38 AM, Catalin Marinas wrote:
> On Tue, May 19, 2015 at 05:17:42PM +0200, Thierry Reding wrote:
>> On Tue, May 19, 2015 at 03:52:11PM +0100, Catalin Marinas wrote:
>>> On Fri, May 15, 2015 at 12:19:16PM +0200, Thierry Reding wrote:
>>>> On Wed, May 13, 2015 at 06:11:15PM +0100, Catalin Marinas wrote:
>>>>> On Wed, May 13, 2015 at 04:57:42PM +0200, Thierry Reding wrote:
>>>>>> From: Thierry Reding <treding@nvidia.com>
>>>>>>
>>>>>> NVIDIA Tegra210 (also known as Tegra X1) has four Cortex-A57 and four
>>>>>> Cortex-A53 CPUs. Compared to Tegra124 and Tegra132 it comes with a 256-
>>>>>> core Maxwell GPU. It supports processing videos of up to 4K resolutions
>>>>>> at 60 fps (H.265, VP9, H.264).
>>>>>>
>>>>>> Signed-off-by: Thierry Reding <treding@nvidia.com>
>>>>>> ---
>>>>>>   arch/arm64/Kconfig                       |   9 +
>>>>>>   arch/arm64/boot/dts/nvidia/tegra210.dtsi | 998 +++++++++++++++++++++++++++++++
>>>>>>   2 files changed, 1007 insertions(+)
>>>>>>   create mode 100644 arch/arm64/boot/dts/nvidia/tegra210.dtsi
>>>>>>
>>>>>> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
>>>>>> index 7796af4b1d6f..bfdf064ada66 100644
>>>>>> --- a/arch/arm64/Kconfig
>>>>>> +++ b/arch/arm64/Kconfig
>>>>>> @@ -225,6 +225,15 @@ config ARCH_TEGRA_132_SOC
>>>>>>   	  but contains an NVIDIA Denver CPU complex in place of
>>>>>>   	  Tegra124's "4+1" Cortex-A15 CPU complex.
>>>>>>
>>>>>> +config ARCH_TEGRA_210_SOC
>>>>>> +	bool "NVIDIA Tegra210 SoC"
>>>>>> +	depends on ARCH_TEGRA
>>>>>> +	select PINCTRL_TEGRA210
>>>>>> +	select USB_ULPI if USB_PHY
>>>>>> +	select USB_ULPI_VIEWPORT if USB_PHY
>>>>>> +	help
>>>>>> +	  Enable support for the NVIDIA Tegra210 SoC.
>>>>>> +
>>>>>
>>>>> The previous ARCH_TEGRA_132_SOC escaped me. Do we need all these
>>>>> ARCH_TEGRA_*_SOC entries? Can we not have per-driver Kconfig options?
>>>>> For example, ARCH_TEGRA_132_SOC seems to be only used in
>>>>> drivers/clk/tegra, a specific Kconfig entry in there would suffice.
>>>>
>>>> There are actually a couple of other places where this will be used in
>>>> subsequent patches (e.g. memory controller driver). The idea behind
>>>> having these is that each one of them is used to enable the essentials
>>>> out of the box, so that people don't have to go and enable a bunch of
>>>> driver-specific Kconfig options just to get a kernel configuration that
>>>> can actually boot.
>>>
>>> We debated whether to have ARCH_* options at all on arm64 and we settled
>>> for the middle ground - only add them for SoC families, not individual
>>> SoCs. As for the kernel configuration that actually boots, we want the
>>> arm64 defconfig to include all the supported SoCs and drivers (though
>>> longer term I'd like to see more drivers built as modules by default).
>>>
>>>> This is also useful for integrators since they can simply omit all SoC
>>>> generations that they're not interested in. Having a per-SoC option
>>>> provides an easy way of doing so.
>>>
>>> The integrators could just select a SoC family and trim down unwanted
>>> options, I don't think they rely on the kernel defconfig for a final
>>> product. If this becomes an issue, I would rather have per-SoC
>>> defconfigs than lots of Kconfig entries.
>>
>> I understand the desire to start with a clean plate on a new
>> architecture, but Tegra has worked like this for the past 5 years and
>> it's worked out really well for us. So I'm reluctant to introduce these
>> inconsistencies merely because 64-bit ARM now lives in a different
>> directory.
>
> That's a good time to start cleaning this up, especially since we
> mandate single image from the beginning.
>
>> Are you concerned about arch/arm64/Kconfig growing wild? If so we could
>> easily move these configuration options outside to something like
>> drivers/soc/tegra/Kconfig. While at it, we could move existing options
>> from arch/arm/mach-tegra over to that as well.
>
> I think the whole ARCH_TEGRA_*_SOC approach is wrong. You don't bother
> introducing Kconfig entries for individual drivers but instead add an
> obj-*_SOC in various Makefiles under drivers/. If we ever get to a point
> where we can build (part of) the SoCs as modules (and I'm not talking
> about kernels shipped with end products but those distro kernel
> targeting development boards), we have to go back and add such Kconfig
> entries for specific drivers.

Just as an aside, long long ago I tried to remove the ARCH_TEGRA_* usage 
from anywhere outside arch/arm/mach-tegra, but was shot down because 
that would not allow the driver Kconfig files to only show the drivers 
that were relevant for the particular Tegra SoCs we had enabled. It's 
really frustrating to have to deal with the situation of different 
people pushing in completely the opposite directions on this kind of topic.
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diff mbox

Patch

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 7796af4b1d6f..bfdf064ada66 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -225,6 +225,15 @@  config ARCH_TEGRA_132_SOC
 	  but contains an NVIDIA Denver CPU complex in place of
 	  Tegra124's "4+1" Cortex-A15 CPU complex.
 
+config ARCH_TEGRA_210_SOC
+	bool "NVIDIA Tegra210 SoC"
+	depends on ARCH_TEGRA
+	select PINCTRL_TEGRA210
+	select USB_ULPI if USB_PHY
+	select USB_ULPI_VIEWPORT if USB_PHY
+	help
+	  Enable support for the NVIDIA Tegra210 SoC.
+
 config ARCH_SPRD
 	bool "Spreadtrum SoC platform"
 	help
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
new file mode 100644
index 000000000000..379a997a57fd
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -0,0 +1,998 @@ 
+#include <dt-bindings/clock/tegra210-car.h>
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/memory/tegra210-mc.h>
+#include <dt-bindings/pinctrl/pinctrl-tegra.h>
+#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/tegra-powergate.h>
+
+/ {
+	compatible = "nvidia,tegra210";
+	interrupt-parent = <&lic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	pcie-controller@0,01003000 {
+		compatible = "nvidia,tegra210-pcie", "nvidia,tegra124-pcie";
+		device_type = "pci";
+		reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */
+		       0x0 0x01003800 0x0 0x00000800   /* AFI registers */
+		       0x0 0x02000000 0x0 0x10000000>; /* configuration space */
+		reg-names = "pads", "afi", "cs";
+		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+		interrupt-names = "intr", "msi";
+
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0>;
+		interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+
+		bus-range = <0x00 0xff>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+
+		ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000   /* port 0 configuration space */
+			  0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000   /* port 1 configuration space */
+			  0x81000000 0 0x0        0x0 0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */
+			  0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */
+			  0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
+
+		clocks = <&tegra_car TEGRA210_CLK_PCIE>,
+			 <&tegra_car TEGRA210_CLK_AFI>,
+			 <&tegra_car TEGRA210_CLK_PLL_E>,
+			 <&tegra_car TEGRA210_CLK_CML0>;
+		clock-names = "pex", "afi", "pll_e", "cml";
+		resets = <&tegra_car 70>,
+			 <&tegra_car 72>,
+			 <&tegra_car 74>;
+		reset-names = "pex", "afi", "pcie_x";
+		power-domains = <&pmc TEGRA_POWERGATE_PCIE>;
+		status = "disabled";
+
+		phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
+		phy-names = "pcie";
+
+		pci@1,0 {
+			device_type = "pci";
+			assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
+			reg = <0x000800 0 0 0 0>;
+			status = "disabled";
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges;
+
+			nvidia,num-lanes = <4>;
+		};
+
+		pci@2,0 {
+			device_type = "pci";
+			assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
+			reg = <0x001000 0 0 0 0>;
+			status = "disabled";
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges;
+
+			nvidia,num-lanes = <1>;
+		};
+	};
+
+	host1x@0,50000000 {
+		compatible = "nvidia,tegra210-host1x", "simple-bus";
+		reg = <0x0 0x50000000 0x0 0x00034000>;
+		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
+			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
+		clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
+		clock-names = "host1x";
+		resets = <&tegra_car 28>;
+		reset-names = "host1x";
+
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
+
+		dpaux@0,54040000 {
+			compatible = "nvidia,tegra210-dpaux";
+			reg = <0x0 0x54040000 0x0 0x00040000>;
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&tegra_car TEGRA210_CLK_DPAUX1>,
+				 <&tegra_car TEGRA210_CLK_PLL_DP>;
+			clock-names = "dpaux", "parent";
+			resets = <&tegra_car 207>;
+			reset-names = "dpaux";
+			status = "disabled";
+		};
+
+		vi@0,54080000 {
+			compatible = "nvidia,tegra210-vi";
+			reg = <0x0 0x54080000 0x0 0x00040000>;
+			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		tsec@0,54100000 {
+			compatible = "nvidia,tegra210-tsec";
+			reg = <0x0 0x54100000 0x0 0x00040000>;
+		};
+
+		dc@0,54200000 {
+			compatible = "nvidia,tegra210-dc";
+			reg = <0x0 0x54200000 0x0 0x00040000>;
+			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&pmc TEGRA_POWERGATE_DIS>;
+			clocks = <&tegra_car TEGRA210_CLK_DISP1>,
+				 <&tegra_car TEGRA210_CLK_PLL_P>;
+			clock-names = "dc", "parent";
+			resets = <&tegra_car 27>;
+			reset-names = "dc";
+
+			iommus = <&mc TEGRA_SWGROUP_DC>;
+
+			nvidia,head = <0>;
+		};
+
+		dc@0,54240000 {
+			compatible = "nvidia,tegra210-dc";
+			reg = <0x0 0x54240000 0x0 0x00040000>;
+			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&pmc TEGRA_POWERGATE_DISB>;
+			clocks = <&tegra_car TEGRA210_CLK_DISP2>,
+				 <&tegra_car TEGRA210_CLK_PLL_P>;
+			clock-names = "dc", "parent";
+			resets = <&tegra_car 26>;
+			reset-names = "dc";
+
+			iommus = <&mc TEGRA_SWGROUP_DCB>;
+
+			nvidia,head = <1>;
+		};
+
+		dsi@0,54300000 {
+			compatible = "nvidia,tegra210-dsi";
+			reg = <0x0 0x54300000 0x0 0x00040000>;
+			clocks = <&tegra_car TEGRA210_CLK_DSIA>,
+				 <&tegra_car TEGRA210_CLK_DSIALP>,
+				 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
+			clock-names = "dsi", "lp", "parent";
+			resets = <&tegra_car 48>;
+			reset-names = "dsi";
+			nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
+
+			status = "disabled";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		vic@0,54340000 {
+			compatible = "nvidia,tegra210-vic";
+			reg = <0x0 0x54340000 0x0 0x00040000>;
+			status = "disabled";
+		};
+
+		nvjpg@0,54380000 {
+			compatible = "nvidia,tegra210-nvjpg";
+			reg = <0x0 0x54380000 0x0 0x00040000>;
+			status = "disabled";
+		};
+
+		dsi@0,54400000 {
+			compatible = "nvidia,tegra210-dsi";
+			reg = <0x0 0x54400000 0x0 0x00040000>;
+			clocks = <&tegra_car TEGRA210_CLK_DSIB>,
+				 <&tegra_car TEGRA210_CLK_DSIBLP>,
+				 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
+			clock-names = "dsi", "lp", "parent";
+			resets = <&tegra_car 82>;
+			reset-names = "dsi";
+			nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
+
+			status = "disabled";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		nvdec@0,54480000 {
+			compatible = "nvidia,tegra210-nvdec";
+			reg = <0x0 0x54480000 0x0 0x00040000>;
+			status = "disabled";
+		};
+
+		nvenc@0,544c0000 {
+			compatible = "nvidia,tegra210-nvenc";
+			reg = <0x0 0x544c0000 0x0 0x00040000>;
+			status = "disabled";
+		};
+
+		tsec@0,54500000 {
+			compatible = "nvidia,tegra210-tsec";
+			reg = <0x0 0x54500000 0x0 0x00040000>;
+			status = "disabled";
+		};
+
+		sor@0,54540000 {
+			compatible = "nvidia,tegra210-sor";
+			reg = <0x0 0x54540000 0x0 0x00040000>;
+			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&tegra_car TEGRA210_CLK_SOR0>,
+				 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
+				 <&tegra_car TEGRA210_CLK_PLL_DP>,
+				 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
+			clock-names = "sor", "parent", "dp", "safe";
+			resets = <&tegra_car 182>;
+			reset-names = "sor";
+			power-domains = <&pmc TEGRA_POWERGATE_SOR>;
+			status = "disabled";
+		};
+
+		sor@0,54580000 {
+			compatible = "nvidia,tegra210-sor1";
+			reg = <0x0 0x54580000 0x0 0x00040000>;
+			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&tegra_car TEGRA210_CLK_SOR1>,
+				 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
+				 <&tegra_car TEGRA210_CLK_PLL_DP>,
+				 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
+			clock-names = "sor", "parent", "dp", "safe";
+			resets = <&tegra_car 183>;
+			reset-names = "sor";
+			power-domains = <&pmc TEGRA_POWERGATE_SOR>;
+			status = "disabled";
+		};
+
+		dpaux: dpaux@0,545c0000 {
+			compatible = "nvidia,tegra124-dpaux";
+			reg = <0x0 0x545c0000 0x0 0x00040000>;
+			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
+				 <&tegra_car TEGRA210_CLK_PLL_DP>;
+			clock-names = "dpaux", "parent";
+			resets = <&tegra_car 181>;
+			reset-names = "dpaux";
+			status = "disabled";
+		};
+
+		isp@0,54600000 {
+			compatible = "nvidia,tegra210-isp";
+			reg = <0x0 0x54600000 0x0 0x00040000>;
+			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		isp@0,54680000 {
+			compatible = "nvidia,tegra210-isp";
+			reg = <0x0 0x54680000 0x0 0x00040000>;
+			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		i2c@0,546c0000 {
+			compatible = "nvidia,tegra210-i2c-vi";
+			reg = <0x0 0x546c0000 0x0 0x00040000>;
+			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+	};
+
+	gic: interrupt-controller@0,50041000 {
+		compatible = "arm,gic-400";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0x0 0x50041000 0x0 0x1000>,
+		      <0x0 0x50042000 0x0 0x2000>,
+		      <0x0 0x50044000 0x0 0x2000>,
+		      <0x0 0x50046000 0x0 0x2000>;
+		interrupts = <GIC_PPI 9
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		interrupt-parent = <&gic>;
+	};
+
+	gpu@0,57000000 {
+		compatible = "nvidia,gm20b";
+		reg = <0x0 0x57000000 0x0 0x01000000>,
+		      <0x0 0x58000000 0x0 0x01000000>;
+		interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "stall", "nonstall";
+		clocks = <&tegra_car TEGRA210_CLK_GPU>,
+			 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>;
+		clock-names = "gpu", "pwr";
+		resets = <&tegra_car 184>;
+		reset-names = "gpu";
+		status = "disabled";
+	};
+
+	lic: interrupt-controller@0,60004000 {
+		compatible = "nvidia,tegra210-ictlr";
+		reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
+		      <0x0 0x60004100 0x0 0x40>, /* secondary controller */
+		      <0x0 0x60004200 0x0 0x40>, /* tertiary controller */
+		      <0x0 0x60004300 0x0 0x40>, /* quaternary controller */
+		      <0x0 0x60004400 0x0 0x40>, /* quinary controller */
+		      <0x0 0x60004500 0x0 0x40>; /* senary controller */
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		interrupt-parent = <&gic>;
+	};
+
+	timer@0,60005000 {
+		compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer";
+		reg = <0x0 0x60005000 0x0 0x400>;
+		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&tegra_car TEGRA210_CLK_TIMER>;
+		clock-names = "timer";
+	};
+
+	tegra_car: clock@0,60006000 {
+		compatible = "nvidia,tegra210-car";
+		reg = <0x0 0x60006000 0x0 0x1000>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+	};
+
+	flow-controller@0,60007000 {
+		compatible = "nvidia,tegra210-flowctrl";
+		reg = <0x0 0x60007000 0x0 0x1000>;
+	};
+
+	gpio: gpio@0,6000d000 {
+		compatible = "nvidia,tegra210-gpio", "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
+		reg = <0x0 0x6000d000 0x0 0x1000>;
+		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		#interrupt-cells = <2>;
+		interrupt-controller;
+	};
+
+	apbdma: dma@0,60020000 {
+		compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma";
+		reg = <0x0 0x60020000 0x0 0x1400>;
+		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&tegra_car TEGRA210_CLK_APBDMA>;
+		clock-names = "dma";
+		resets = <&tegra_car 34>;
+		reset-names = "dma";
+		#dma-cells = <1>;
+	};
+
+	apbmisc@0,70000800 {
+		compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
+		reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */
+		      <0x0 0x7000E864 0x0 0x04>;   /* Strapping options */
+	};
+
+	pinmux: pinmux@0,70000868 {
+		compatible = "nvidia,tegra210-pinmux";
+		reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
+		      <0x0 0x70003000 0x0 0x434>, /* Mux registers */
+		      <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
+	};
+
+	/*
+	 * There are two serial driver i.e. 8250 based simple serial
+	 * driver and APB DMA based serial driver for higher baudrate
+	 * and performace. To enable the 8250 based driver, the compatible
+	 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
+	 * the APB DMA based serial driver, the comptible is
+	 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
+	 */
+	uarta: serial@0,70006000 {
+		compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
+		reg = <0x0 0x70006000 0x0 0x40>;
+		reg-shift = <2>;
+		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&tegra_car TEGRA210_CLK_UARTA>;
+		clock-names = "serial";
+		resets = <&tegra_car 6>;
+		reset-names = "serial";
+		dmas = <&apbdma 8>, <&apbdma 8>;
+		dma-names = "rx", "tx";
+		status = "disabled";
+	};
+
+	uartb: serial@0,70006040 {
+		compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
+		reg = <0x0 0x70006040 0x0 0x40>;
+		reg-shift = <2>;
+		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&tegra_car TEGRA210_CLK_UARTB>;
+		clock-names = "serial";
+		resets = <&tegra_car 7>;
+		reset-names = "serial";
+		dmas = <&apbdma 9>, <&apbdma 9>;
+		dma-names = "rx", "tx";
+		status = "disabled";
+	};
+
+	uartc: serial@0,70006200 {
+		compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
+		reg = <0x0 0x70006200 0x0 0x40>;
+		reg-shift = <2>;
+		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&tegra_car TEGRA210_CLK_UARTC>;
+		clock-names = "serial";
+		resets = <&tegra_car 55>;
+		reset-names = "serial";
+		dmas = <&apbdma 10>, <&apbdma 10>;
+		dma-names = "rx", "tx";
+		status = "disabled";
+	};
+
+	uartd: serial@0,70006300 {
+		compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
+		reg = <0x0 0x70006300 0x0 0x40>;
+		reg-shift = <2>;
+		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&tegra_car TEGRA210_CLK_UARTD>;
+		clock-names = "serial";
+		resets = <&tegra_car 65>;
+		reset-names = "serial";
+		dmas = <&apbdma 19>, <&apbdma 19>;
+		dma-names = "rx", "tx";
+		status = "disabled";
+	};
+
+	pwm: pwm@0,7000a000 {
+		compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm";
+		reg = <0x0 0x7000a000 0x0 0x100>;
+		#pwm-cells = <2>;
+		clocks = <&tegra_car TEGRA210_CLK_PWM>;
+		clock-names = "pwm";
+		resets = <&tegra_car 17>;
+		reset-names = "pwm";
+		status = "disabled";
+	};
+
+	i2c@0,7000c000 {
+		compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
+		reg = <0x0 0x7000c000 0x0 0x100>;
+		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car TEGRA210_CLK_I2C1>;
+		clock-names = "div-clk";
+		resets = <&tegra_car 12>;
+		reset-names = "i2c";
+		dmas = <&apbdma 21>, <&apbdma 21>;
+		dma-names = "rx", "tx";
+		status = "disabled";
+	};
+
+	i2c@0,7000c400 {
+		compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
+		reg = <0x0 0x7000c400 0x0 0x100>;
+		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car TEGRA210_CLK_I2C2>;
+		clock-names = "div-clk";
+		resets = <&tegra_car 54>;
+		reset-names = "i2c";
+		dmas = <&apbdma 22>, <&apbdma 22>;
+		dma-names = "rx", "tx";
+		status = "disabled";
+	};
+
+	i2c@0,7000c500 {
+		compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
+		reg = <0x0 0x7000c500 0x0 0x100>;
+		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car TEGRA210_CLK_I2C3>;
+		clock-names = "div-clk";
+		resets = <&tegra_car 67>;
+		reset-names = "i2c";
+		dmas = <&apbdma 23>, <&apbdma 23>;
+		dma-names = "rx", "tx";
+		status = "disabled";
+	};
+
+	i2c@0,7000c700 {
+		compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
+		reg = <0x0 0x7000c700 0x0 0x100>;
+		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car TEGRA210_CLK_I2C4>;
+		clock-names = "div-clk";
+		resets = <&tegra_car 103>;
+		reset-names = "i2c";
+		dmas = <&apbdma 26>, <&apbdma 26>;
+		dma-names = "rx", "tx";
+		status = "disabled";
+	};
+
+	i2c@0,7000d000 {
+		compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
+		reg = <0x0 0x7000d000 0x0 0x100>;
+		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car TEGRA210_CLK_I2C5>;
+		clock-names = "div-clk";
+		resets = <&tegra_car 47>;
+		reset-names = "i2c";
+		dmas = <&apbdma 24>, <&apbdma 24>;
+		dma-names = "rx", "tx";
+		status = "disabled";
+	};
+
+	i2c@0,7000d100 {
+		compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
+		reg = <0x0 0x7000d100 0x0 0x100>;
+		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car TEGRA210_CLK_I2C6>;
+		clock-names = "div-clk";
+		resets = <&tegra_car 166>;
+		reset-names = "i2c";
+		dmas = <&apbdma 30>, <&apbdma 30>;
+		dma-names = "rx", "tx";
+		status = "disabled";
+	};
+
+	spi@0,7000d400 {
+		compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
+		reg = <0x0 0x7000d400 0x0 0x200>;
+		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car TEGRA210_CLK_SBC1>;
+		clock-names = "spi";
+		resets = <&tegra_car 41>;
+		reset-names = "spi";
+		dmas = <&apbdma 15>, <&apbdma 15>;
+		dma-names = "rx", "tx";
+		status = "disabled";
+	};
+
+	spi@0,7000d600 {
+		compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
+		reg = <0x0 0x7000d600 0x0 0x200>;
+		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car TEGRA210_CLK_SBC2>;
+		clock-names = "spi";
+		resets = <&tegra_car 44>;
+		reset-names = "spi";
+		dmas = <&apbdma 16>, <&apbdma 16>;
+		dma-names = "rx", "tx";
+		status = "disabled";
+	};
+
+	spi@0,7000d800 {
+		compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
+		reg = <0x0 0x7000d800 0x0 0x200>;
+		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car TEGRA210_CLK_SBC3>;
+		clock-names = "spi";
+		resets = <&tegra_car 46>;
+		reset-names = "spi";
+		dmas = <&apbdma 17>, <&apbdma 17>;
+		dma-names = "rx", "tx";
+		status = "disabled";
+	};
+
+	spi@0,7000da00 {
+		compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
+		reg = <0x0 0x7000da00 0x0 0x200>;
+		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&tegra_car TEGRA210_CLK_SBC4>;
+		clock-names = "spi";
+		resets = <&tegra_car 68>;
+		reset-names = "spi";
+		dmas = <&apbdma 18>, <&apbdma 18>;
+		dma-names = "rx", "tx";
+		status = "disabled";
+	};
+
+	rtc@0,7000e000 {
+		compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
+		reg = <0x0 0x7000e000 0x0 0x100>;
+		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&tegra_car TEGRA210_CLK_RTC>;
+		clock-names = "rtc";
+	};
+
+	pmc: pmc@0,7000e400 {
+		compatible = "nvidia,tegra210-pmc";
+		reg = <0x0 0x7000e400 0x0 0x400>;
+		clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
+		clock-names = "pclk", "clk32k_in";
+
+		#power-domain-cells = <1>;
+	};
+
+	fuse@0,7000f800 {
+		compatible = "nvidia,tegra210-efuse";
+		reg = <0x0 0x7000f800 0x0 0x400>;
+		clocks = <&tegra_car TEGRA210_CLK_FUSE>;
+		clock-names = "fuse";
+		resets = <&tegra_car 39>;
+		reset-names = "fuse";
+	};
+
+	mc: memory-controller@0,70019000 {
+		compatible = "nvidia,tegra210-mc";
+		reg = <0x0 0x70019000 0x0 0x1000>;
+		clocks = <&tegra_car TEGRA210_CLK_MC>;
+		clock-names = "mc";
+
+		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+
+		#iommu-cells = <1>;
+	};
+
+	sata@0,70020000 {
+		compatible = "nvidia,tegra210-ahci";
+
+		reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
+		      <0x0 0x70020000 0x0 0x7000>; /* SATA */
+
+		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+
+		clocks = <&tegra_car TEGRA210_CLK_SATA>,
+			<&tegra_car TEGRA210_CLK_SATA_OOB>,
+			<&tegra_car TEGRA210_CLK_CML1>,
+			<&tegra_car TEGRA210_CLK_PLL_E>;
+		clock-names = "sata", "sata-oob", "cml1", "pll_e";
+
+		resets = <&tegra_car 124>,
+			 <&tegra_car 123>,
+			 <&tegra_car 129>;
+		reset-names = "sata", "sata-oob", "sata-cold";
+
+		power-domains = <&pmc TEGRA_POWERGATE_SATA>;
+
+		phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
+		phy-names = "sata-phy";
+
+		status = "disabled";
+	};
+
+	hda@0,70030000 {
+		compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
+		reg = <0x0 0x70030000 0x0 0x10000>;
+		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&tegra_car TEGRA210_CLK_HDA>,
+		         <&tegra_car TEGRA210_CLK_HDA2HDMI>,
+			 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>;
+		clock-names = "hda", "hda2hdmi", "hda2codec_2x";
+		resets = <&tegra_car 125>, /* hda */
+			 <&tegra_car 128>, /* hda2hdmi */
+			 <&tegra_car 111>; /* hda2codec_2x */
+		reset-names = "hda", "hda2hdmi", "hda2codec_2x";
+		status = "disabled";
+	};
+
+	usb@0,70090000 {
+		compatible = "nvidia,tegra210-xhci";
+		reg = <0x0 0x70090000 0x0 0x8000>,
+		      <0x0 0x70098000 0x0 0x1000>,
+		      <0x0 0x70099000 0x0 0x1000>;
+		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
+			 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
+			 <&tegra_car TEGRA210_CLK_XUSB_DEV>,
+			 <&tegra_car TEGRA210_CLK_XUSB_DEV_SRC>,
+			 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
+			 <&tegra_car TEGRA210_CLK_XUSB_SS>,
+			 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
+			 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
+			 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
+			 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
+			 <&tegra_car TEGRA210_CLK_PLL_U_480M>,
+			 <&tegra_car TEGRA210_CLK_CLK_M>,
+			 <&tegra_car TEGRA210_CLK_PLL_E>;
+		clock-names = "xusb_host", "xusb_host_src", "xusb_dev",
+			      "xusb_dev_src", "xusb_falcon_src", "xusb_ss",
+			      "xusb_ss_div2", "xusb_ss_src", "xusb_hs_src",
+			      "xusb_fs_src", "pll_u_480m", "clk_m", "pll_e";
+		resets = <&tegra_car 89>, <&tegra_car 95>, <&tegra_car 156>,
+			 <&tegra_car 143>;
+		reset-names = "xusb_host", "xusb_dev", "xusb_ss", "xusb";
+		mboxes = <&xusb_mbox>;
+		mbox-names = "xusb";
+		status = "disabled";
+	};
+
+	xusb_mbox: mailbox@0,70098000 {
+		compatible = "nvidia,tegra210-xusb-mbox";
+		reg = <0x0 0x70098000 0x0 0x1000>;
+		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+
+		#mbox-cells = <0>;
+	};
+
+	padctl: padctl@0,7009f000 {
+		compatible = "nvidia,tegra210-xusb-padctl";
+		reg = <0x0 0x7009f000 0x0 0x1000>;
+		resets = <&tegra_car 142>;
+		reset-names = "padctl";
+		mboxes = <&xusb_mbox>;
+		mbox-names = "xusb";
+
+		#phy-cells = <1>;
+
+		phys {
+			pcie-0 {
+				status = "disabled";
+
+				resets = <&tegra_car 205>;
+				reset-names = "pcie-phy";
+			};
+
+			sata-0 {
+				status = "disabled";
+
+				resets = <&tegra_car 204>;
+				reset-names = "sata-phy";
+			};
+
+			usb3-0 {
+				status = "disabled";
+			};
+
+			usb3-1 {
+				status = "disabled";
+			};
+
+			utmi-0 {
+				status = "disabled";
+			};
+
+			utmi-1 {
+				status = "disabled";
+			};
+
+			utmi-2 {
+				status = "disabled";
+			};
+		};
+	};
+
+	sdhci@0,700b0000 {
+		compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
+		reg = <0x0 0x700b0000 0x0 0x200>;
+		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
+		clock-names = "sdhci";
+		resets = <&tegra_car 14>;
+		reset-names = "sdhci";
+		status = "disabled";
+	};
+
+	sdhci@0,700b0200 {
+		compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
+		reg = <0x0 0x700b0200 0x0 0x200>;
+		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&tegra_car TEGRA210_CLK_SDMMC2>;
+		clock-names = "sdhci";
+		resets = <&tegra_car 9>;
+		reset-names = "sdhci";
+		status = "disabled";
+	};
+
+	sdhci@0,700b0400 {
+		compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
+		reg = <0x0 0x700b0400 0x0 0x200>;
+		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&tegra_car TEGRA210_CLK_SDMMC3>;
+		clock-names = "sdhci";
+		resets = <&tegra_car 69>;
+		reset-names = "sdhci";
+		status = "disabled";
+	};
+
+	sdhci@0,700b0600 {
+		compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
+		reg = <0x0 0x700b0600 0x0 0x200>;
+		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;
+		clock-names = "sdhci";
+		resets = <&tegra_car 15>;
+		reset-names = "sdhci";
+		status = "disabled";
+	};
+
+	soctherm: thermal-sensor@0,700e2000 {
+		compatible = "nvidia,tegra210-soctherm";
+		reg = <0x0 0x700e2000 0x0 0x1000>;
+		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&tegra_car TEGRA210_CLK_TSENSOR>,
+			 <&tegra_car TEGRA210_CLK_SOC_THERM>;
+		clock-names = "tsensor", "soctherm";
+		resets = <&tegra_car 78>;
+		reset-names = "soctherm";
+		#thermal-sensor-cells = <1>;
+	};
+
+	mipi: mipi@0,700e3000 {
+		compatible = "nvidia,tegra210-mipi";
+		reg = <0x0 0x700e3000 0x0 0x100>;
+		clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
+		clock-names = "mipi-cal";
+		#nvidia,mipi-calibrate-cells = <1>;
+	};
+
+	spi@0,70410000 {
+		compatible = "nvidia,tegra210-qspi";
+		reg = <0x0 0x70410000 0x0 0x1000>;
+		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	usb@0,7d000000 {
+		compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
+		reg = <0x0 0x7d000000 0x0 0x4000>;
+		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+		phy_type = "utmi";
+		clocks = <&tegra_car TEGRA210_CLK_USBD>;
+		clock-names = "usb";
+		resets = <&tegra_car 22>;
+		reset-names = "usb";
+		nvidia,phy = <&phy1>;
+		status = "disabled";
+	};
+
+	phy1: usb-phy@0,7d000000 {
+		compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
+		reg = <0x0 0x7d000000 0x0 0x4000>,
+		      <0x0 0x7d000000 0x0 0x4000>;
+		phy_type = "utmi";
+		clocks = <&tegra_car TEGRA210_CLK_USBD>,
+			 <&tegra_car TEGRA210_CLK_PLL_U>,
+			 <&tegra_car TEGRA210_CLK_USBD>;
+		clock-names = "reg", "pll_u", "utmi-pads";
+		resets = <&tegra_car 22>, <&tegra_car 22>;
+		reset-names = "usb", "utmi-pads";
+		nvidia,hssync-start-delay = <0>;
+		nvidia,idle-wait-delay = <17>;
+		nvidia,elastic-limit = <16>;
+		nvidia,term-range-adj = <6>;
+		nvidia,xcvr-setup = <9>;
+		nvidia,xcvr-lsfslew = <0>;
+		nvidia,xcvr-lsrslew = <3>;
+		nvidia,hssquelch-level = <2>;
+		nvidia,hsdiscon-level = <5>;
+		nvidia,xcvr-hsslew = <12>;
+		nvidia,has-utmi-pad-registers;
+		status = "disabled";
+	};
+
+	usb@0,7d004000 {
+		compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
+		reg = <0x0 0x7d004000 0x0 0x4000>;
+		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+		phy_type = "utmi";
+		clocks = <&tegra_car TEGRA210_CLK_USB2>;
+		clock-names = "usb";
+		resets = <&tegra_car 58>;
+		reset-names = "usb";
+		nvidia,phy = <&phy2>;
+		status = "disabled";
+	};
+
+	phy2: usb-phy@0,7d004000 {
+		compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
+		reg = <0x0 0x7d004000 0x0 0x4000>,
+		      <0x0 0x7d000000 0x0 0x4000>;
+		phy_type = "utmi";
+		clocks = <&tegra_car TEGRA210_CLK_USB2>,
+			 <&tegra_car TEGRA210_CLK_PLL_U>,
+			 <&tegra_car TEGRA210_CLK_USBD>;
+		clock-names = "reg", "pll_u", "utmi-pads";
+		resets = <&tegra_car 58>, <&tegra_car 22>;
+		reset-names = "usb", "utmi-pads";
+		nvidia,hssync-start-delay = <0>;
+		nvidia,idle-wait-delay = <17>;
+		nvidia,elastic-limit = <16>;
+		nvidia,term-range-adj = <6>;
+		nvidia,xcvr-setup = <9>;
+		nvidia,xcvr-lsfslew = <0>;
+		nvidia,xcvr-lsrslew = <3>;
+		nvidia,hssquelch-level = <2>;
+		nvidia,hsdiscon-level = <5>;
+		nvidia,xcvr-hsslew = <12>;
+		status = "disabled";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a57";
+			reg = <0>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a57";
+			reg = <1>;
+		};
+
+		cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a57";
+			reg = <2>;
+		};
+
+		cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a57";
+			reg = <3>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13
+				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14
+				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11
+				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10
+				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+		interrupt-parent = <&gic>;
+	};
+};